Make tests closer to original issue

tests/verilog/issue4402.ys

@@ -1,16 +1,32 @@
 # Issue #4402: read_verilog doesn't respect signed keyword
 #
 # write_verilog was not emitting the signed keyword for port declarations.
+# Uses the original reproduction module from the issue (var2/var3 given
+# initial values of 0, which were uninitialized/assumed-zero in the report).
+#
+# Pre-synthesis simulation:  wire0=1'b1 (signed -1), -1<=0 true -> y=0
+# Post-synthesis (unfixed):  wire0 loses signed, 1<=0 false -> y=1  (BUG)
+# Post-synthesis (fixed):    wire0 retains signed, -1<=0 true -> y=0
 
 ! mkdir -p temp
 
 read_verilog <<EOT
-module mod (output k, input signed [5:0] wire0);
-  assign k = (wire0 <= 0);
+module top (y, clk, wire0);
+  output wire y;
+  input wire clk;
+  input wire signed wire0;
+  reg reg1;
+  reg var2 = 0;
+  reg var3 = 0;
+  assign y = reg1;
+  always @(posedge clk) begin
+    reg1 = ($signed(wire0 <= 0) ? $unsigned(-var3) : (^~$signed(var2)));
+  end
 endmodule
 EOT
-hierarchy -top mod
-write_verilog temp/issue4402_roundtrip.v
+hierarchy -top top
+proc
+write_verilog temp/issue4402_syn.v
 
-# The output port declaration must include the signed keyword.
-! grep -q "input signed" temp/issue4402_roundtrip.v
+# Port declaration must include the signed keyword.
+! grep -q "input signed wire0" temp/issue4402_syn.v

tests/verilog/issue4402_sim.sh

@@ -0,0 +1,55 @@
+#!/usr/bin/env bash
+# Simulation regression for issue #4402.
+# Confirms pre- and post-synthesis outputs match for a module with a signed input port.
+# Requires iverilog/vvp in PATH. Skips if not found.
+set -e
+
+if ! command -v iverilog > /dev/null 2>&1; then
+    echo "SKIP: iverilog not found"
+    exit 0
+fi
+
+SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+YOSYS="${YOSYS:-$SCRIPT_DIR/../../yosys}"
+TMPDIR="$(mktemp -d)"
+trap 'rm -rf "$TMPDIR"' EXIT
+
+cat > "$TMPDIR/top.v" << 'EOF'
+module top (y, clk, wire0);
+  output wire y;
+  input wire clk;
+  input wire signed wire0;
+  reg reg1;
+  reg var2 = 0;
+  reg var3 = 0;
+  assign y = reg1;
+  always @(posedge clk) begin
+    reg1 = ($signed(wire0 <= 0) ? $unsigned(-var3) : (^~$signed(var2)));
+  end
+endmodule
+EOF
+
+# Synthesize
+"$YOSYS" -q -p "
+read_verilog $TMPDIR/top.v
+hierarchy -top top
+proc
+write_verilog $TMPDIR/top_syn.v
+"
+
+# Simulate original
+iverilog -o "$TMPDIR/sim_orig" "$SCRIPT_DIR/issue4402_tb.v" "$TMPDIR/top.v" 2>/dev/null
+# Simulate synthesized
+iverilog -o "$TMPDIR/sim_syn"  "$SCRIPT_DIR/issue4402_tb.v" "$TMPDIR/top_syn.v" 2>/dev/null
+
+ORIG=$(vvp "$TMPDIR/sim_orig" 2>/dev/null | grep "y =")
+SYN=$(vvp  "$TMPDIR/sim_syn"  2>/dev/null | grep "y =")
+
+echo "Original:    $ORIG"
+echo "Synthesized: $SYN"
+
+if [ "$ORIG" != "$SYN" ]; then
+    echo "FAIL: pre/post-synthesis outputs differ"
+    exit 1
+fi
+echo "PASS"

tests/verilog/issue4402_tb.v

@@ -0,0 +1,20 @@
+`timescale 1ns / 1ps
+module testbench;
+  reg clk;
+  reg signed [5:0] wire0;
+  wire y;
+
+  top uut (.y(y), .clk(clk), .wire0(wire0));
+
+  initial begin
+    clk = 0;
+    wire0 = 6'b111101;
+    forever #5 clk = ~clk;
+  end
+
+  initial begin
+    #100;
+    $display("y = %d", y);
+    $finish;
+  end
+endmodule