# Issue #4402: read_verilog doesn't respect signed keyword
#
# write_verilog was not emitting the signed keyword for port declarations.
# Uses the original reproduction module from the issue (var2/var3 given
# initial values of 0, which were uninitialized/assumed-zero in the report).
#
# Pre-synthesis simulation:  wire0=1'b1 (signed -1), -1<=0 true -> y=0
# Post-synthesis (unfixed):  wire0 loses signed, 1<=0 false -> y=1  (BUG)
# Post-synthesis (fixed):    wire0 retains signed, -1<=0 true -> y=0

! mkdir -p temp

read_verilog <<EOT
module top (y, clk, wire0);
  output wire y;
  input wire clk;
  input wire signed wire0;
  reg reg1;
  reg var2 = 0;
  reg var3 = 0;
  assign y = reg1;
  always @(posedge clk) begin
    reg1 = ($signed(wire0 <= 0) ? $unsigned(-var3) : (^~$signed(var2)));
  end
endmodule
EOT
hierarchy -top top
proc
write_verilog temp/issue4402_syn.v

# Port declaration must include the signed keyword.
! grep -q "input signed wire0" temp/issue4402_syn.v