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yosys/tests/simple
2020-09-21 15:07:02 +02:00
..
.gitignore
aes_kexp128.v
always01.v
always02.v
always03.v
arraycells.v
arrays01.v Added test cases from 2012 paper on comparison of foss verilog synthesis tools 2013-03-31 11:17:56 +02:00
arrays02.sv
attrib01_module.v
attrib02_port_decl.v
attrib03_parameter.v
attrib04_net_var.v
attrib05_port_conn.v.DISABLED
attrib06_operator_suffix.v
attrib07_func_call.v.DISABLED
attrib08_mod_inst.v
attrib09_case.v
carryadd.v
const_branch_finish.v Propagate const_fold through generate blocks and branches 2020-08-09 17:21:08 -04:00
constmuldivmod.v Expand tests/simple/constmuldivmod.v 2020-05-28 22:59:04 +02:00
constpower.v
defvalue.sv
dff_different_styles.v
dff_init.v
dynslice.v
fiedler-cooley.v initial import 2013-01-05 11:13:26 +01:00
forgen01.v
forgen02.v
forloops.v
fsm.v
generate.v Module name scope support 2020-08-20 20:15:08 -04:00
graphtest.v Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
hierarchy.v
hierdefparam.v
i2c_master_tests.v
implicit_ports.v
localparam_attr.v
loops.v
macros.v
mem2reg.v
mem_arst.v
memory.v
multiplier.v
muxtree.v
omsp_dbg_uart.v
operators.v
param_attr.v
paramods.v
partsel.v Bugfix in partsel.v signed indices test cases 2020-05-02 11:21:01 +02:00
process.v
realexpr.v
repwhile.v
retime.v
rotate.v
run-test.sh tests/simple: remove "nullglob" shopt 2020-09-21 15:07:02 +02:00
scopes.v
signedexpr.v
sincos.v
specify.v
string_format.v Allow %0s $display format specifier 2020-08-09 17:19:49 -04:00
subbytes.v
task_func.v
undef_eqx_nex.v
usb_phy_tests.v
values.v
vloghammer.v
wandwor.v
wreduce.v
xfirrtl