Zachary Snow c016f6a423 proc_rmdead: use explicit pattern set when there are no wildcards ... If width of a case expression was large, explicit patterns could cause the existing logic to take an extremely long time, or exhaust the maximum size of the underlying set. For cases where all of the patterns are fully defined and there are no constants in the case expression, this change uses a simple set to track which patterns have been seen.		2021-07-29 20:55:59 -04:00
..
.gitignore
aes_kexp128.v
always01.v
always02.v
always03.v
arraycells.v
arrays01.v
arrays02.sv
asgn_binop.sv	sv: support remaining assignment operators	2021-05-25 16:15:57 -04:00
attrib01_module.v
attrib02_port_decl.v
attrib03_parameter.v
attrib04_net_var.v
attrib05_port_conn.v.DISABLED
attrib06_operator_suffix.v
attrib07_func_call.v.DISABLED
attrib08_mod_inst.v
attrib09_case.v
carryadd.v
case_expr_const.v	verilog: fix case expression sign and width handling	2021-05-25 16:16:46 -04:00
case_expr_non_const.v	verilog: fix case expression sign and width handling	2021-05-25 16:16:46 -04:00
case_large.v	proc_rmdead: use explicit pattern set when there are no wildcards	2021-07-29 20:55:59 -04:00
const_branch_finish.v	Fix begin/end in generate	2020-11-11 12:03:37 +09:00
const_fold_func.v	verilog: refactored constant function evaluation	2021-02-04 10:18:27 -05:00
const_func_shadow.v	verilog: refactored constant function evaluation	2021-02-04 10:18:27 -05:00
constmuldivmod.v	Expand tests/simple/constmuldivmod.v	2020-05-28 22:59:04 +02:00
constpower.v
defvalue.sv
dff_different_styles.v
dff_init.v
dynslice.v
fiedler-cooley.v
forgen01.v
forgen02.v
forloops.v
fsm.v
func_block.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
func_recurse.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
func_width_scope.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
genblk_collide.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
genblk_dive.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
genblk_order.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
genblk_port_shadow.v	verlog: allow shadowing module ports within generate blocks	2021-02-07 11:48:39 -05:00
generate.v	Merge pull request #2529 from zachjs/unnamed-genblk	2021-02-04 09:57:28 +00:00
graphtest.v
hierarchy.v
hierdefparam.v
i2c_master_tests.v
ifdef_1.v	verilog: fix handling of nested ifdef directives	2021-03-01 12:28:33 -05:00
ifdef_2.v	verilog: fix handling of nested ifdef directives	2021-03-01 12:28:33 -05:00
implicit_ports.v
local_loop_var.sv	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
localparam_attr.v
loop_prefix_case.v	genrtlil: add width detection for AST_PREFIX nodes	2021-07-29 20:55:31 -04:00
loop_var_shadow.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
loops.v
macro_arg_spaces.sv	verilog: allow spaces in macro arguments	2021-01-20 08:49:58 -07:00
macro_arg_surrounding_spaces.v	verilog: strip leading and trailing spaces in macro args	2021-01-28 11:26:35 -05:00
macros.v
matching_end_labels.sv	sv: fix up end label checking	2021-06-16 21:48:05 -04:00
mem2reg.v
mem2reg_bounds_tern.v	mem2reg: tolerate out of bounds constant accesses	2021-06-08 15:02:57 -04:00
mem_arst.v
memory.v
module_scope.v	verilog: support module scope identifiers in parametric modules	2021-03-16 11:01:30 -04:00
module_scope_case.v	verilog: check for module scope identifiers during width detection	2021-06-08 15:03:16 -04:00
multiplier.v
muxtree.v
named_genblk.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
nested_genblk_resolve.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
omsp_dbg_uart.v
operators.v
param_attr.v
paramods.v
partsel.v
process.v
realexpr.v
repwhile.v
retime.v
rotate.v
run-test.sh	tests/simple: remove "nullglob" shopt	2020-09-21 15:07:02 +02:00
scopes.v
signedexpr.v
sincos.v
specify.v
string_format.v	Allow %0s $display format specifier	2020-08-09 17:19:49 -04:00
subbytes.v
task_func.v
undef_eqx_nex.v
unnamed_block_decl.sv	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
usb_phy_tests.v
values.v
verilog_primitives.v	verilog: fix buf/not primitives with multiple outputs	2021-03-17 11:44:03 -04:00
vloghammer.v	More deadname stuff	2021-06-09 12:33:41 +02:00
wandwor.v
wreduce.v
xfirrtl