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yosys/tests/simple
Zachary Snow 1ec5994100 verilog: fix handling of nested ifdef directives
- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
2021-03-01 12:28:33 -05:00
..
.gitignore
aes_kexp128.v
always01.v
always02.v
always03.v
arraycells.v
arrays01.v
arrays02.sv
attrib01_module.v
attrib02_port_decl.v
attrib03_parameter.v
attrib04_net_var.v
attrib05_port_conn.v.DISABLED
attrib06_operator_suffix.v
attrib07_func_call.v.DISABLED
attrib08_mod_inst.v
attrib09_case.v
carryadd.v
const_branch_finish.v Fix begin/end in generate 2020-11-11 12:03:37 +09:00
const_fold_func.v verilog: refactored constant function evaluation 2021-02-04 10:18:27 -05:00
const_func_shadow.v verilog: refactored constant function evaluation 2021-02-04 10:18:27 -05:00
constmuldivmod.v
constpower.v
defvalue.sv
dff_different_styles.v
dff_init.v
dynslice.v
fiedler-cooley.v
forgen01.v
forgen02.v
forloops.v
fsm.v
func_block.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
func_recurse.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
func_width_scope.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
genblk_collide.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
genblk_dive.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
genblk_order.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
genblk_port_shadow.v verlog: allow shadowing module ports within generate blocks 2021-02-07 11:48:39 -05:00
generate.v Merge pull request #2529 from zachjs/unnamed-genblk 2021-02-04 09:57:28 +00:00
graphtest.v
hierarchy.v
hierdefparam.v
i2c_master_tests.v
ifdef_1.v verilog: fix handling of nested ifdef directives 2021-03-01 12:28:33 -05:00
ifdef_2.v verilog: fix handling of nested ifdef directives 2021-03-01 12:28:33 -05:00
implicit_ports.v
local_loop_var.sv verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
localparam_attr.v
loop_var_shadow.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
loops.v
macro_arg_spaces.sv verilog: allow spaces in macro arguments 2021-01-20 08:49:58 -07:00
macro_arg_surrounding_spaces.v verilog: strip leading and trailing spaces in macro args 2021-01-28 11:26:35 -05:00
macros.v
mem2reg.v
mem_arst.v
memory.v
multiplier.v
muxtree.v
named_genblk.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
nested_genblk_resolve.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
omsp_dbg_uart.v
operators.v
param_attr.v
paramods.v
partsel.v
process.v
realexpr.v
repwhile.v
retime.v
rotate.v
run-test.sh tests/simple: remove "nullglob" shopt 2020-09-21 15:07:02 +02:00
scopes.v
signedexpr.v
sincos.v
specify.v
string_format.v Allow %0s $display format specifier 2020-08-09 17:19:49 -04:00
subbytes.v
task_func.v
undef_eqx_nex.v
unnamed_block_decl.sv verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
usb_phy_tests.v
values.v
vloghammer.v
wandwor.v
wreduce.v
xfirrtl