Eddie Hung 5bba9c3640 ast: fixes #1710; do not generate RTLIL for unreachable ternary		2020-02-27 16:55:55 -08:00
..
.gitignore
abc9.v	Another sloppy mistake!	2019-11-21 16:33:20 -08:00
abc9.ys	write_xaiger: fix for (* keep *) on flop output	2020-01-21 09:43:04 -08:00
async.sh
async.v
attrib05_port_conn.v
attrib05_port_conn.ys
attrib07_func_call.v
attrib07_func_call.ys
autoname.ys	autoname: add testcase with $-prefix-ed port	2020-01-14 10:13:03 -08:00
bug1480.ys	Fix #1462, #1480.	2019-11-19 08:57:39 +01:00
bug1496.ys	Fix #1496.	2019-11-18 04:16:48 +01:00
bug1531.ys	Add testcase	2019-12-11 16:52:37 -08:00
bug1614.ys	add testcase for #1614	2020-02-03 21:29:54 +01:00
bug1710.ys	ast: fixes #1710; do not generate RTLIL for unreachable ternary	2020-02-27 16:55:55 -08:00
chparam.sh
constmsk_test.v
constmsk_test.ys
constmsk_testmap.v
elab_sys_tasks.sv
elab_sys_tasks.ys
equiv_opt_multiclock.ys
gzip_verilog.v.gz
gzip_verilog.ys
help.ys	Add "help -all" and "help -celltypes" sanity test	2020-01-28 18:11:34 -08:00
hierarchy.sh
hierarchy_defer.ys
mem2reg.ys
muxcover.ys
muxpack.v
muxpack.ys
peepopt.ys
pmgen_reduce.ys
pmux2shiftx.v
pmux2shiftx.ys
reg_wire_error.sv
reg_wire_error.ys
run-test.sh
scratchpad.ys	add assert option to scratchpad command	2019-12-16 14:00:21 +01:00
script.ys
sformatf.ys	ast: Add support for $sformatf system function	2020-01-19 21:20:17 +00:00
shregmap.v
shregmap.ys
signext.ys
specify.v	verilog: ignore ranges too without -specify	2020-02-13 17:58:43 -08:00
specify.ys	clean: ignore specify-s inside cells when determining whether to keep	2020-02-19 10:45:10 -08:00
submod_extract.ys
sv_implicit_ports.sh	sv: More tests for wildcard port connections	2020-02-02 16:12:33 +00:00
svalways.sh	sv: Add tests for SV always types	2019-11-21 21:06:28 +00:00
wreduce.ys
write_gzip.ys