Emil J. Tywoniak ed7e50be24 tests: exclude signorm marker cells from cell-count assertions		2026-07-22 01:22:17 +02:00
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bug2619.ys
bug2656.ys
bug2962.ys
bug4712.ys	tests/proc: add proc_dff bug 4712 as testcase	2024-11-07 00:10:17 +01:00
bug5572.ys	Test empty switches	2026-01-07 13:21:33 +13:00
bug_1268.v
bug_1268.ys
case_attr.ys	tests: add cases covering full_case and parallel_case semantics	2025-05-29 20:45:57 -06:00
clean_undef_case.ys
generate_mk.py	Converted some more	2026-04-16 11:00:44 +02:00
proc_dff.ys
proc_dlatch.ys	Fixup issue test.	2026-06-15 16:23:44 +02:00
proc_latches.ys	Fixup level policy.	2026-06-18 18:00:51 +02:00
proc_mux_src.v	proc_mux, genrtlil: make use of case_src for better case condition vs block tracking	2026-07-20 15:01:30 +02:00
proc_mux_src.ys	proc_mux: include switch expression location in $eq src	2026-07-20 15:01:30 +02:00
proc_rom.ys
rmdead.v
rmdead.ys
rmdead_case_x.ys	Add tests.	2026-06-25 11:14:54 +02:00
yosys_latch.sv	Add tests.	2026-06-15 15:46:13 +02:00
yosys_latch.ys	tests: exclude signorm marker cells from cell-count assertions	2026-07-22 01:22:17 +02:00