This website requires JavaScript.
Explore
Help
Register
Sign in
mirrors
/
yosys
Watch
3
Star
0
Fork
You've already forked yosys
0
mirror of
https://github.com/YosysHQ/yosys
synced
2026-04-15 16:54:12 +00:00
Code
Activity
a53104379d
yosys
/
techlibs
/
common
History
Robert O'Callahan
e87bb65956
Move
Design::sort()
calls out of
opt
and
opt_clean
passes into the synth passes that need them.
2026-01-23 01:14:35 +00:00
..
choices
.gitignore
abc9_map.v
abc9_model.v
abc9_unmap.v
adff2dff.v
cellhelp.py
cmp2lcu.v
cmp2lut.v
cmp2softlogic.v
dff2ff.v
gate2lut.v
gen_fine_ffs.py
Makefile.inc
mul2dsp.v
opensta.cc
opensta.h
pmux2mux.v
prep.cc
sdc_expand.cc
simcells.v
simlib.v
smtmap.v
synth.cc
techmap.v