Emil J. Tywoniak 0c450ce8c8 WIP migration to twine		2026-06-18 19:27:41 +02:00
..
tests	Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.	2025-07-22 10:38:38 +00:00
abc9_model.v
arith_map.v
brams_defs.vh
brams_xc2v.txt
brams_xc2v_map.v
brams_xc3sda.txt
brams_xc3sda_map.v
brams_xc4v.txt
brams_xc4v_map.v
brams_xc5v_map.v
brams_xc6v_map.v	Fix RAMB36E1/E2 SDP parity port mapping typo	2026-04-18 19:10:18 +03:00
brams_xcu_map.v	Fix RAMB36E1/E2 SDP parity port mapping typo	2026-04-18 19:10:18 +03:00
brams_xcv.txt
brams_xcv_map.v
cells_map.v	Clearer diff for the all-x corner case	2025-04-07 07:55:30 +02:00
cells_sim.v
cells_xtra.py
cells_xtra.v	Add and use fix_mod.py	2026-01-28 07:45:58 +13:00
ff_map.v
lut_map.v
lutrams_xc5v.txt
lutrams_xc5v_map.v
lutrams_xcu.txt
lutrams_xcv.txt
lutrams_xcv_map.v
Makefile.inc	pmgen: Move passes out of pmgen folder	2025-01-31 15:18:28 +13:00
mux_map.v
synth_xilinx.cc	Add check before flatten in synth_*.	2026-05-05 14:06:58 +02:00
urams.txt	URAM mapping : Add test for 2048 x 144b	2025-05-10 14:53:56 +02:00
urams_map.v	URAM mapping : Fix port indexes according to Yosys warnings	2025-05-09 15:09:11 +02:00
xc3s_mult_map.v
xc3sda_dsp_map.v
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_dsp_map.v
xc7_dsp_map.v
xcu_dsp_map.v
xilinx_dffopt.cc	WIP migration to twine	2026-06-18 19:27:41 +02:00
xilinx_dsp.cc	WIP migration to twine	2026-06-18 19:27:41 +02:00
xilinx_dsp.pmg	WIP migration to twine	2026-06-18 19:27:41 +02:00
xilinx_dsp48a.pmg	WIP migration to twine	2026-06-18 19:27:41 +02:00
xilinx_dsp_cascade.pmg	WIP migration to twine	2026-06-18 19:27:41 +02:00
xilinx_dsp_CREG.pmg	WIP migration to twine	2026-06-18 19:27:41 +02:00
xilinx_srl.cc	WIP migration to twine	2026-06-18 19:27:41 +02:00
xilinx_srl.pmg	WIP migration to twine	2026-06-18 19:27:41 +02:00