Eddie Hung f11dd6e208 tests: add a quick plugin test		2020-04-09 09:45:20 -07:00
..
.gitignore	tests: add a quick plugin test	2020-04-09 09:45:20 -07:00
abc9.v
abc9.ys
async.sh
async.v
attrib05_port_conn.v
attrib05_port_conn.ys
attrib07_func_call.v
attrib07_func_call.ys
autoname.ys
bug1496.ys
bug1531.ys
bug1614.ys
bug1710.ys
bug1745.ys	Add regression tests for new handling of comments in constants	2020-03-14 11:41:09 +01:00
bug1781.ys	fsm_extract: Initialize celltypes with full design.	2020-03-19 18:51:21 +01:00
chparam.sh
constcomment.ys	Add regression tests for new handling of comments in constants	2020-03-14 11:41:09 +01:00
constmsk_test.v
constmsk_test.ys
constmsk_testmap.v
deminout_unused.ys
elab_sys_tasks.sv
elab_sys_tasks.ys
equiv_opt_multiclock.ys
exec.ys	Add test for exec command.	2020-03-16 07:52:58 +00:00
gzip_verilog.v.gz
gzip_verilog.ys
help.ys
hierarchy.sh
hierarchy_defer.ys
ice40_mince_abc9.ys	Add test for abc9+mince issue	2020-03-20 20:35:28 +00:00
logger_error.ys
logger_nowarning.ys
logger_warn.ys
logger_warning.ys
mem2reg.ys
muxcover.ys
muxpack.v
muxpack.ys
peepopt.ys
plugin.cc	tests: add a quick plugin test	2020-04-09 09:45:20 -07:00
plugin.sh	tests: add a quick plugin test	2020-04-09 09:45:20 -07:00
pmgen_reduce.ys
pmux2shiftx.v
pmux2shiftx.ys
reg_wire_error.sv
reg_wire_error.ys
run-test.sh
scratchpad.ys
script.ys
sformatf.ys
shregmap.v
shregmap.ys
signext.ys
specify.v
specify.ys
src.ys
submod.ys
submod_extract.ys
sv_defines.ys	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
sv_defines_dup.ys	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
sv_defines_mismatch.ys	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
sv_defines_too_few.ys	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
sv_implicit_ports.sh
svalways.sh
wreduce.ys
write_gzip.ys