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yosys/tests
2026-03-18 17:59:58 +01:00
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aiger
alumacc
arch Add missing EOL 2026-03-06 09:10:55 +01:00
asicworld
bind
blif
bram
bugpoint
cxxrtl
errors
fmt
fsm
functional
hana
liberty
lut
memfile
memlib
memories
opt Add test that connects a wire with init to a constant 2026-03-06 02:20:08 +00:00
opt_share
peepopt
proc
pyosys Remove todo. 2026-03-04 12:39:45 +01:00
realmath
rpc
rtlil
sat
sdc
select
share
sim
simple
simple_abc9
smv
sva
svinterfaces
svtypes ast: Add support for array-to-array assignment 2026-03-04 21:34:40 -08:00
techmap synth: fix after abc -fast removal 2026-03-18 17:59:58 +01:00
tools Add 'init' attributes to RTLIL fuzzing 2026-03-06 02:20:08 +00:00
unit Add unit tests for ConcurrentWorkQueue 2026-03-06 02:20:08 +00:00
various Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors 2026-02-25 15:39:31 +01:00
verific tests/verific: ensure mixed -f requires VHDL unit 2026-01-28 22:46:10 -08:00
verilog support automatic lifetime qualifier on procedural variables 2026-02-27 20:42:52 +03:00
vloghtb
xprop
.gitignore
common-env.sh
gen-tests-makefile.sh
pass-fuzzing.md