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Code Activity
yosys/frontends/verilog
History
Gary Wong 5feb1a1752 verilog: add support for SystemVerilog string literals. 
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-03 20:51:12 -06:00
..
.gitignore
const2ast.cc
Makefile.inc
preproc.cc
preproc.h
verilog_frontend.cc
verilog_frontend.h
verilog_lexer.l verilog: add support for SystemVerilog string literals. 2025-07-03 20:51:12 -06:00
verilog_parser.y verilog: fix parser "if" memory errors. 2025-06-22 23:57:42 -04:00