Eddie Hung 7a62ee57b4 Merge pull request #2024 from YosysHQ/eddie/primitive_src ... verilog: set src attribute for primitives		2020-05-05 06:49:18 -07:00
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aiger
arch
asicworld
bram
errors
fsm
hana
liberty
lut
memfile
memories
opt
opt_share
proc
realmath
rpc
sat
select
share
simple
simple_abc9
smv
sva
svinterfaces
svtypes
techmap
tools
unit
various	Merge pull request #2024 from YosysHQ/eddie/primitive_src	2020-05-05 06:49:18 -07:00
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