Dag Lem a32d9b6c45 Fix test of memory vs. memory converted to registers ... The purpose of memtest02 in tests/simple/memory.v is to test bit select on both memory (mem1) and memory converted to registers (mem2). After 7cfae2c52, mem1 was automatically converted to registers, and the test no longer worked as intended. This is fixed by adding (* nomem2reg *) to mem1.		2024-02-11 11:26:52 -05:00
..
.gitignore
aes_kexp128.v
always01.v
always02.v
always03.v
arraycells.v
arrays01.v
arrays02.sv	Add proper test for SV-style arrays	2019-06-20 12:06:07 +02:00
asgn_binop.sv	sv: support remaining assignment operators	2021-05-25 16:15:57 -04:00
attrib01_module.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
attrib02_port_decl.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
attrib03_parameter.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
attrib04_net_var.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
attrib05_port_conn.v.DISABLED	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
attrib06_operator_suffix.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
attrib07_func_call.v.DISABLED	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
attrib08_mod_inst.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
attrib09_case.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
carryadd.v
case_expr_const.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
case_expr_extend.sv	fix iverilog compatibility for new case expr tests	2022-01-03 12:11:41 -07:00
case_expr_non_const.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
case_expr_query.sv	fix iverilog compatibility for new case expr tests	2022-01-03 12:11:41 -07:00
case_large.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
const_branch_finish.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
const_fold_func.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
const_func_shadow.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
constmuldivmod.v	Expand tests/simple/constmuldivmod.v	2020-05-28 22:59:04 +02:00
constpower.v
defvalue.sv	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
dff_different_styles.v
dff_init.v
dynslice.v	Add dynamic slicing Verilog testcase	2020-03-31 11:51:31 -07:00
fiedler-cooley.v
forgen01.v
forgen02.v
forloops.v
fsm.v
func_block.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
func_recurse.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
func_width_scope.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
genblk_collide.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
genblk_dive.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
genblk_order.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
genblk_port_shadow.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
generate.v	Merge pull request #2529 from zachjs/unnamed-genblk	2021-02-04 09:57:28 +00:00
graphtest.v
hierarchy.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
hierdefparam.v	Fix valgrind tests when using verific	2022-03-30 17:25:53 +02:00
i2c_master_tests.v
ifdef_1.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
ifdef_2.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
implicit_ports.sv	Fix valgrind tests when using verific	2022-03-30 17:25:53 +02:00
lesser_size_cast.sv	sv: fix size cast clipping expression width	2022-01-03 08:17:35 -07:00
local_loop_var.sv	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
localparam_attr.v	Added tests for Verilog frontent for attributes on parameters and localparams	2019-05-16 12:53:43 +02:00
loop_prefix_case.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
loop_var_shadow.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
loops.v
macro_arg_spaces.sv	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
macro_arg_surrounding_spaces.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
macros.v
matching_end_labels.sv	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
mem2reg.v
mem2reg_bounds_tern.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
mem_arst.v	Make SV2017 compliant courtesy of @wsnyder	2019-12-12 07:34:07 -08:00
memory.v	Fix test of memory vs. memory converted to registers	2024-02-11 11:26:52 -05:00
memwr_port_connection.sv	verilog: use derived module info to elaborate cell connections	2021-10-25 18:25:50 -07:00
module_scope.v	Fix valgrind tests when using verific	2022-03-30 17:25:53 +02:00
module_scope_case.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
module_scope_func.v	verilog: Support module-scoped task/function calls	2022-10-29 15:14:11 -04:00
multiplier.v
muxtree.v
named_genblk.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
nested_genblk_resolve.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
omsp_dbg_uart.v
operators.v
param_attr.v	Added tests for Verilog frontent for attributes on parameters and localparams	2019-05-16 12:53:43 +02:00
paramods.v
partsel.v	test: add tests for shiftadd and shiftmul	2023-11-06 14:01:37 +01:00
process.v
realexpr.v	Add test case for real parameters	2019-08-20 11:38:21 +02:00
repwhile.v
retime.v
rotate.v
run-test.sh	tests: use /usr/bin/env for bash.	2023-08-12 11:59:39 +10:00
scopes.v
sign_part_assign.v	Add test for rhs sign extension in array slice assignment	2024-01-10 21:15:00 +01:00
signed_full_slice.v	verilog: use derived module info to elaborate cell connections	2021-10-25 18:25:50 -07:00
signedexpr.v
sincos.v
specify.v	Fix valgrind tests when using verific	2022-03-30 17:25:53 +02:00
string_format.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
subbytes.v
task_func.v
undef_eqx_nex.v
unnamed_block_decl.sv	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
usb_phy_tests.v
values.v
verilog_primitives.v	verilog: fix buf/not primitives with multiple outputs	2021-03-17 11:44:03 -04:00
vloghammer.v	More deadname stuff	2021-06-09 12:33:41 +02:00
wandwor.v	Fix "make vgtest" so it runs to the end (but now it fails ;)	2021-09-23 14:54:28 +02:00
wreduce.v
xfirrtl	Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.	2019-07-31 09:27:38 -07:00