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Code Activity
yosys/frontends
History
Zachary Snow 83cd19678e verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections 
- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.
2026-01-13 16:42:09 +01:00
..
aiger Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
aiger2 Enable xaiger2 pass when not in NDEBUG 2025-11-21 14:23:32 -08:00
ast verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections 2026-01-13 16:42:09 +01:00
blif Forbid creating IdStrings and incrementing autoidx during multithreaded phases, and add dynamic checks for that 2025-11-25 21:57:46 +00:00
json Use fast path for 32-bit Const integer constructor in more places 2025-09-16 03:17:24 +00:00
liberty read_liberty: support loopy retention cells 2025-11-20 13:21:32 +01:00
rpc Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
rtlil Add -legalize option to read_rtlil 2025-12-21 21:47:48 +00:00
verific avoid merging formal properties 2025-12-17 20:25:24 +01:00
verilog no use vector 2025-11-08 23:16:52 +05:30