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yosys/frontends/ast
History
Zachary Snow 83cd19678e verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections 
- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.
2026-01-13 16:42:09 +01:00
..
ast.cc Add CONST_FLAG_UNSIZED 2025-11-07 17:45:07 +13:00
ast.h Make AstNode::input_error use C++ stringf machinery 2025-09-12 06:01:32 +00:00
ast_binding.cc Generate an RTLIL representation of bind constructs 2021-08-13 17:11:35 -06:00
ast_binding.h Generate an RTLIL representation of bind constructs 2021-08-13 17:11:35 -06:00
dpicall.cc Remove .c_str() calls from log()/log_error() 2025-09-11 20:59:37 +00:00
genrtlil.cc verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections 2026-01-13 16:42:09 +01:00
Makefile.inc Generate an RTLIL representation of bind constructs 2021-08-13 17:11:35 -06:00
simplify.cc verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections 2026-01-13 16:42:09 +01:00