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yosys/tests/arch/analogdevices
Krystine Sherwin 805f110aef analogdevices: Extra tests
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
2025-10-18 12:14:03 +01:00
..
.gitignore analogdevices: Extra tests 2025-10-18 12:14:03 +01:00
abc9_dff.ys test suite 2025-10-16 08:43:08 +01:00
add_sub.ys test suite 2025-10-16 08:43:08 +01:00
adffs.ys test suite 2025-10-16 08:43:08 +01:00
asym_ram_sdp.ys test suite 2025-10-16 08:43:08 +01:00
asym_ram_sdp_read_wider.v test suite 2025-10-16 08:43:08 +01:00
asym_ram_sdp_write_wider.v test suite 2025-10-16 08:43:08 +01:00
attributes_test.ys test suite 2025-10-16 08:43:08 +01:00
blockram.ys test suite 2025-10-16 08:43:08 +01:00
bug1460.ys test suite 2025-10-16 08:43:08 +01:00
bug1462.ys test suite 2025-10-16 08:43:08 +01:00
bug1480.ys test suite 2025-10-16 08:43:08 +01:00
bug1598.ys test suite 2025-10-16 08:43:08 +01:00
bug1605.ys test suite 2025-10-16 08:43:08 +01:00
bug3670.v test suite 2025-10-16 08:43:08 +01:00
bug3670.ys test suite 2025-10-16 08:43:08 +01:00
counter.ys test suite 2025-10-16 08:43:08 +01:00
dffs.ys test suite 2025-10-16 08:43:08 +01:00
dsp_abc9.ys test suite 2025-10-16 08:43:08 +01:00
fsm.ys test suite 2025-10-16 08:43:08 +01:00
logic.ys test suite 2025-10-16 08:43:08 +01:00
lutram.ys analogdevices: Extra tests 2025-10-18 12:14:03 +01:00
macc.sh test suite 2025-10-16 08:43:08 +01:00
macc.v test suite 2025-10-16 08:43:08 +01:00
macc.ys test suite 2025-10-16 08:43:08 +01:00
macc_tb.v test suite 2025-10-16 08:43:08 +01:00
mem_gen.py analogdevices: Extra tests 2025-10-18 12:14:03 +01:00
mul.ys analogdevices: DSP inference 2025-10-16 23:33:59 +01:00
mul_unsigned.v test suite 2025-10-16 08:43:08 +01:00
mul_unsigned.ys test suite 2025-10-16 08:43:08 +01:00
mux.ys test suite 2025-10-16 08:43:08 +01:00
opt_lut_ins.ys test suite 2025-10-16 08:43:08 +01:00
run-test.sh analogdevices: Extra tests 2025-10-18 12:14:03 +01:00
shifter.ys test suite 2025-10-16 08:43:08 +01:00
tribuf.ys test suite 2025-10-16 08:43:08 +01:00