Krystine Sherwin 7f12d0ba95 QLF_TDP36K: more basic tdp/sdp sim tests ... Adds TDP submodule to generator. Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).		2023-12-04 15:52:03 +01:00
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.gitignore	quicklogic: Initial blockram tests	2023-12-04 15:52:03 +01:00
add_sub.ys	quicklogic: Add basic k6n10f tests	2023-12-04 15:52:03 +01:00
adffs.ys	quicklogic: Add basic k6n10f tests	2023-12-04 15:52:03 +01:00
bram_tdp.v	add example memory test	2023-12-04 15:52:03 +01:00
bram_tdp.ys	QLF_TDP36K: test bram_tdp post synth	2023-12-04 15:52:03 +01:00
bram_tdp_tb.v	QLF_TDP36K: test bram_tdp post synth	2023-12-04 15:52:03 +01:00
counter.ys	quicklogic: Add basic k6n10f tests	2023-12-04 15:52:03 +01:00
dffs.ys	quicklogic: Fix dffs.ys test	2023-12-04 15:52:03 +01:00
dsp.ys	quicklogic: Add k6n10f DSP test	2023-12-04 15:52:03 +01:00
fsm.ys	quicklogic: Add basic k6n10f tests	2023-12-04 15:52:03 +01:00
gen_memories.py	QLF_TDP36K: more basic tdp/sdp sim tests	2023-12-04 15:52:03 +01:00
latches.ys	quicklogic: Add basic k6n10f tests	2023-12-04 15:52:03 +01:00
logic.ys	quicklogic: Add basic k6n10f tests	2023-12-04 15:52:03 +01:00
mem_tb.v	QLF_TDP36K: more basic tdp/sdp sim tests	2023-12-04 15:52:03 +01:00
mux.ys	quicklogic: Add basic k6n10f tests	2023-12-04 15:52:03 +01:00
run-test.sh	quicklogic: Add basic k6n10f tests	2023-12-04 15:52:03 +01:00