Rupert Swarbrick 044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend ... This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.		2020-03-27 16:08:26 +00:00
..
.gitignore
abc9.v
abc9.ys	write_xaiger: fix for (* keep *) on flop output	2020-01-21 09:43:04 -08:00
async.sh
async.v
attrib05_port_conn.v
attrib05_port_conn.ys
attrib07_func_call.v
attrib07_func_call.ys
autoname.ys
bug1496.ys
bug1531.ys
bug1614.ys	add testcase for #1614	2020-02-03 21:29:54 +01:00
bug1710.ys	ast: fixes #1710; do not generate RTLIL for unreachable ternary	2020-02-27 16:55:55 -08:00
bug1745.ys	Add regression tests for new handling of comments in constants	2020-03-14 11:41:09 +01:00
bug1781.ys	fsm_extract: Initialize celltypes with full design.	2020-03-19 18:51:21 +01:00
chparam.sh
constcomment.ys	Add regression tests for new handling of comments in constants	2020-03-14 11:41:09 +01:00
constmsk_test.v
constmsk_test.ys
constmsk_testmap.v
deminout_unused.ys	deminout: Don't demote inouts with unused bits	2020-03-04 18:44:38 +00:00
elab_sys_tasks.sv
elab_sys_tasks.ys
equiv_opt_multiclock.ys
exec.ys	Add test for exec command.	2020-03-16 07:52:58 +00:00
gzip_verilog.v.gz
gzip_verilog.ys
help.ys	Add "help -all" and "help -celltypes" sanity test	2020-01-28 18:11:34 -08:00
hierarchy.sh
hierarchy_defer.ys
ice40_mince_abc9.ys	Add test for abc9+mince issue	2020-03-20 20:35:28 +00:00
logger_error.ys	Added back tests for logger	2020-03-13 15:00:18 +01:00
logger_nowarning.ys	Added back tests for logger	2020-03-13 15:00:18 +01:00
logger_warn.ys	Added back tests for logger	2020-03-13 15:00:18 +01:00
logger_warning.ys	Added back tests for logger	2020-03-13 15:00:18 +01:00
mem2reg.ys	Change attribute search value to specify precise location instead of simple line number.	2020-02-24 01:39:36 +00:00
muxcover.ys
muxpack.v
muxpack.ys
peepopt.ys
pmgen_reduce.ys
pmux2shiftx.v	Cleanup tests	2020-02-27 10:17:29 -08:00
pmux2shiftx.ys
reg_wire_error.sv
reg_wire_error.ys
run-test.sh
scratchpad.ys
script.ys
sformatf.ys
shregmap.v
shregmap.ys
signext.ys
specify.v	verilog: ignore ranges too without -specify	2020-02-13 17:58:43 -08:00
specify.ys	clean: ignore specify-s inside cells when determining whether to keep	2020-02-19 10:45:10 -08:00
src.ys	verilog: add test	2020-03-11 06:51:03 -07:00
submod.ys
submod_extract.ys
sv_defines.ys	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
sv_defines_dup.ys	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
sv_defines_mismatch.ys	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
sv_defines_too_few.ys	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
sv_implicit_ports.sh	sv: More tests for wildcard port connections	2020-02-02 16:12:33 +00:00
svalways.sh
wreduce.ys
write_gzip.ys