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Code Activity
yosys/frontends
History
Zachary Snow 73cf658996 verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections 
- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.
2025-03-07 20:27:02 +01:00
..
aiger rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
aiger2 aiger2: Clean debug print 2024-12-10 14:27:55 +01:00
ast verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections 2025-03-07 20:27:02 +01:00
blif rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
json fix handling of escaped chars in json backend and frontend 2022-02-18 17:13:09 +01:00
liberty read_liberty: Directly set abc9_box on fitting cells 2024-12-09 15:43:41 +01:00
rpc Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
rtlil read_rtlil: warn on assigns after switches in case rules 2024-11-21 22:41:13 +01:00
verific fix some cases of hdlname being added to objects with private names 2025-01-15 15:56:42 +01:00
verilog verilog_parser: silence yynerrs warning 2024-10-15 08:32:55 -04:00