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yosys/frontends/ast
History
Zachary Snow 73cf658996 verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections 
- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.
2025-03-07 20:27:02 +01:00
..
ast.cc Reduce comparisons of size_t and int 2024-11-29 12:53:29 +13:00
ast.h mark all hash_into methods nodiscard 2025-01-14 12:39:15 +01:00
ast_binding.cc Generate an RTLIL representation of bind constructs 2021-08-13 17:11:35 -06:00
ast_binding.h Generate an RTLIL representation of bind constructs 2021-08-13 17:11:35 -06:00
dpicall.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
genrtlil.cc verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections 2025-03-07 20:27:02 +01:00
Makefile.inc Generate an RTLIL representation of bind constructs 2021-08-13 17:11:35 -06:00
simplify.cc verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections 2025-03-07 20:27:02 +01:00