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dynamic_part_select
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Modifications of tests as per Eddie's request
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2020-04-20 12:45:35 -05:00 |
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.gitignore
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tests: add a quick plugin test
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2020-04-09 09:45:20 -07:00 |
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abc9.v
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Another sloppy mistake!
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2019-11-21 16:33:20 -08:00 |
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abc9.ys
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abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
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2020-05-29 17:17:40 -07:00 |
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async.sh
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Improve tests/various/async, disable failing ffl test
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2019-07-09 22:21:25 +02:00 |
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async.v
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Fix tests/various/async FFL test
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2019-07-09 22:44:39 +02:00 |
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attrib05_port_conn.v
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
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attrib05_port_conn.ys
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
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attrib07_func_call.v
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tests: fix some test warnings
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2020-05-25 10:07:58 -07:00 |
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attrib07_func_call.ys
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
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autoname.ys
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autoname: add testcase with $-prefix-ed port
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2020-01-14 10:13:03 -08:00 |
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bug1496.ys
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Fix #1496.
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2019-11-18 04:16:48 +01:00 |
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bug1531.ys
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Add testcase
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2019-12-11 16:52:37 -08:00 |
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bug1614.ys
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add testcase for #1614
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2020-02-03 21:29:54 +01:00 |
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bug1710.ys
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ast: fixes #1710; do not generate RTLIL for unreachable ternary
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2020-02-27 16:55:55 -08:00 |
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bug1745.ys
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Add regression tests for new handling of comments in constants
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2020-03-14 11:41:09 +01:00 |
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bug1781.ys
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fsm_extract: Initialize celltypes with full design.
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2020-03-19 18:51:21 +01:00 |
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bug1876.ys
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tests: add testcases from #1876
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2020-04-14 12:39:10 -07:00 |
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bug2014.ys
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test: add test for #2014
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2020-05-02 14:22:37 -07:00 |
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chparam.sh
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Add tests/various/chparam.sh
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2019-05-06 16:03:15 +02:00 |
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constcomment.ys
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Add regression tests for new handling of comments in constants
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2020-03-14 11:41:09 +01:00 |
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constmsk_test.v
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Added tests/various/constmsk_test.ys
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2014-09-04 15:07:30 +02:00 |
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constmsk_test.ys
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Added tests/various/constmsk_test.ys
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2014-09-04 15:07:30 +02:00 |
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constmsk_testmap.v
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tests: fix some test warnings
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2020-05-25 10:07:58 -07:00 |
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deminout_unused.ys
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deminout: Don't demote inouts with unused bits
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2020-03-04 18:44:38 +00:00 |
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design.ys
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design: add test
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2020-04-16 12:48:40 -07:00 |
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design1.ys
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design: add test
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2020-04-16 12:48:40 -07:00 |
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design2.ys
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tests: add design -delete tests
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2020-04-16 08:05:18 -07:00 |
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dynamic_part_select.ys
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Remove '-ignore_unknown_cells' option from 'sat'
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2020-04-20 11:58:23 -07:00 |
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elab_sys_tasks.sv
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Initial implementation of elaboration system tasks
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2019-05-03 03:10:43 +03:00 |
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elab_sys_tasks.ys
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Initial implementation of elaboration system tasks
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2019-05-03 03:10:43 +03:00 |
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equiv_opt_multiclock.ys
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Add equiv_opt -multiclock
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2019-09-11 13:55:59 +01:00 |
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exec.ys
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Add test for exec command.
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2020-03-16 07:52:58 +00:00 |
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gen_if_null.v
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verilog: allow null gen-if then block
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2020-05-06 08:43:02 -04:00 |
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gen_if_null.ys
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verilog: allow null gen-if then block
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2020-05-06 08:43:02 -04:00 |
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global_scope.ys
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ast: Fix handling of identifiers in the global scope
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2020-04-16 10:30:07 +01:00 |
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gzip_verilog.v.gz
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Add support for reading gzip'd input files
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2019-07-26 10:23:58 +01:00 |
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gzip_verilog.ys
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Add support for reading gzip'd input files
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2019-07-26 10:23:58 +01:00 |
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help.ys
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Add "help -all" and "help -celltypes" sanity test
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2020-01-28 18:11:34 -08:00 |
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hierarchy.sh
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Fix tests
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2019-04-21 11:40:20 +02:00 |
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hierarchy_defer.ys
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Expand test with `hierarchy' without -auto-top
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2019-09-03 12:17:26 -07:00 |
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hierarchy_param.ys
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hierarchy: Convert positional parameters to named.
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2020-04-21 19:09:00 +02:00 |
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ice40_mince_abc9.ys
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Add test for abc9+mince issue
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2020-03-20 20:35:28 +00:00 |
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logger_error.ys
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Added back tests for logger
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2020-03-13 15:00:18 +01:00 |
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logger_nowarning.ys
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Added back tests for logger
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2020-03-13 15:00:18 +01:00 |
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logger_warn.ys
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Added back tests for logger
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2020-03-13 15:00:18 +01:00 |
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logger_warning.ys
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Added back tests for logger
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2020-03-13 15:00:18 +01:00 |
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mem2reg.ys
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Change attribute search value to specify precise location instead of simple line number.
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2020-02-24 01:39:36 +00:00 |
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muxcover.ys
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Merge origin/master
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2019-06-27 11:20:15 -07:00 |
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muxpack.v
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Add more tests
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2019-06-21 12:31:04 -07:00 |
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muxpack.ys
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Removal of more stat calls from tests
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2019-08-18 21:28:45 -07:00 |
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peepopt.ys
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Use sat -tempinduct and comments for why equiv_opt not sufficient
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2019-10-03 11:11:50 -07:00 |
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plugin.cc
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tests: add a quick plugin test
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2020-04-09 09:45:20 -07:00 |
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plugin.sh
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tests: use yosys-config --datdir instead of hard-coded
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2020-04-22 08:29:45 -07:00 |
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pmgen_reduce.ys
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Add test for pmtest_test "reduce" demo pattern
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2019-08-17 14:05:10 +02:00 |
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pmux2shiftx.v
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Cleanup tests
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2020-02-27 10:17:29 -08:00 |
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pmux2shiftx.ys
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Add #1135 testcase
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2019-06-27 11:02:52 -07:00 |
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primitives.ys
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tests: add tests for primitives' src
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2020-05-04 10:21:47 -07:00 |
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printattr.ys
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printattrs: Add test.
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2020-05-27 08:00:00 +00:00 |
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reg_wire_error.sv
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Modified errors into warnings
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2018-06-05 18:03:22 +03:00 |
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reg_wire_error.ys
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reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
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2018-06-05 18:00:06 +03:00 |
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run-test.sh
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Speed up "make test" and related cleanups
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2019-08-17 14:37:07 +02:00 |
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scratchpad.ys
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add assert option to scratchpad command
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2019-12-16 14:00:21 +01:00 |
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script.ys
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Update test for Pass::call_on_module()
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2019-07-02 08:22:31 -07:00 |
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sformatf.ys
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ast: Add support for $sformatf system function
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2020-01-19 21:20:17 +00:00 |
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shregmap.v
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tests: fix some test warnings
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2020-05-25 10:07:58 -07:00 |
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shregmap.ys
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Remove Xilinx test
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2019-08-22 16:18:07 -07:00 |
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signext.ys
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Extend sign extension tests
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2019-06-20 12:43:59 -07:00 |
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sim_const.ys
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sim: Fix handling of constant-connected cell inputs at startup
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2020-04-21 08:58:52 +01:00 |
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specify.v
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verilog: ignore ranges too without -specify
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2020-02-13 17:58:43 -08:00 |
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specify.ys
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verilog: fix specify src attribute
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2020-05-04 10:53:06 -07:00 |
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src.ys
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verilog: add test
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2020-03-11 06:51:03 -07:00 |
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submod.ys
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Remove submod changes
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2019-12-30 14:56:14 -08:00 |
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submod_extract.ys
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Added tests/various/submod_extract.ys
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2014-07-26 17:22:18 +02:00 |
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sv_defines.ys
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
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sv_defines_dup.ys
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
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sv_defines_mismatch.ys
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
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sv_defines_too_few.ys
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
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sv_implicit_ports.sh
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sv: More tests for wildcard port connections
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2020-02-02 16:12:33 +00:00 |
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svalways.sh
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sv: Add tests for SV always types
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2019-11-21 21:06:28 +00:00 |
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wreduce.ys
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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
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2019-08-12 12:06:45 -07:00 |
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write_gzip.ys
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Do not use Verific in tests/various/write_gzip.ys
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2019-08-16 14:22:46 +02:00 |
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xaiger.ys
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xaiger: add testcase
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2020-05-24 08:48:23 -07:00 |
