mirror of
https://github.com/YosysHQ/yosys
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bbfadc27a1
kernel/compressor_tree.cc, passes/tests/test_kogge_stone.cc, passes/opt/peepopt_shiftpow2.pmg, and techlibs/lattice/lattice_dsp_nexus.pmg (plus the 5 new constids it needs: A0, B0, PIPELINED, SIGNED, SUBTRACT) were all added to main after the emil/twines-proc-srcloc fork point, so no commit in this phase's range ever touches them. They still use the old IdString-based addWire/addCell/setPort/getParam APIs (NEW_ID, plain \X port names) that the twine migration replaces, so they fail to build against current HEAD. Not attributable to any single commit in this phase per task.md's carve-out for genuinely phase-spanning fixes - bundled here as its own commit rather than folded into an unrelated pick. |
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| .. | ||
| tests | ||
| arith_map_ccu2c.v | ||
| arith_map_ccu2d.v | ||
| arith_map_nexus.v | ||
| brams_8kc.txt | ||
| brams_16kd.txt | ||
| brams_map_8kc.v | ||
| brams_map_16kd.v | ||
| brams_map_nexus.v | ||
| brams_nexus.txt | ||
| ccu2c_sim.vh | ||
| ccu2d_sim.vh | ||
| cells_bb_ecp5.v | ||
| cells_bb_nexus.v | ||
| cells_bb_xo2.v | ||
| cells_bb_xo3.v | ||
| cells_bb_xo3d.v | ||
| cells_ff.vh | ||
| cells_io.vh | ||
| cells_map_nexus.v | ||
| cells_map_trellis.v | ||
| cells_sim_ecp5.v | ||
| cells_sim_nexus.v | ||
| cells_sim_xo2.v | ||
| cells_sim_xo3.v | ||
| cells_sim_xo3d.v | ||
| cells_xtra.py | ||
| cells_xtra_nexus.py | ||
| CMakeLists.txt | ||
| common_sim.vh | ||
| dsp_map_18x18.v | ||
| dsp_map_nexus.v | ||
| latches_map.v | ||
| lattice_dsp_nexus.cc | ||
| lattice_dsp_nexus.pmg | ||
| lattice_gsr.cc | ||
| lrams_map_nexus.v | ||
| lrams_nexus.txt | ||
| lutrams_map_nexus.v | ||
| lutrams_map_trellis.v | ||
| lutrams_nexus.txt | ||
| lutrams_trellis.txt | ||
| parse_init.vh | ||
| synth_lattice.cc | ||