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f42923d896
Neither is a cell anything implements. They exist so a mapping rule can
re-emit a multiplier without matching itself, and a later techmap or
`chtype` consumes them. Nothing ever declared them, so
`Cell::port_dir()` fell through to PD_UNKNOWN for every port, and
anything that has to tell a cell's inputs from its outputs had to guess.
signorm guesses "output": setup_driven_wires() skips only PD_INPUT, so
\A and \B of a $__mul are read as drivers. \B is the enclosing module's
own input, already driven by its $input_port cell, and \A is a slice, so
both take the fallback -- interpose a helper wire and connect it -- and
both sides then look driven, which is what a $connect means. _80_mul's
wide branch has two $__mul instances, and it runs `proc; clean` through
_TECHMAP_DO_, whose closing opt_expr normalizes the map design. Result:
four helper wires and four $connect cells manufactured out of a design
that has no multi-driver net in it anywhere.
Declaring them as blackboxes gives the interface a definition without
making them mappable: techmap skips blackbox templates outright
(`tpl->get_blackbox_attribute(ignore_wb)`), and every rule that emits
these types carries an explicit techmap_celltype, so nothing was relying
on matching them by module name.
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| .. | ||
| achronix | ||
| analogdevices | ||
| anlogic | ||
| common | ||
| coolrunner2 | ||
| easic | ||
| efinix | ||
| fabulous | ||
| gatemate | ||
| gowin | ||
| greenpak4 | ||
| ice40 | ||
| intel | ||
| intel_alm | ||
| lattice | ||
| microchip | ||
| nanoxplore | ||
| quicklogic | ||
| sf2 | ||
| xilinx | ||
| CMakeLists.txt | ||
| fix_mod.py | ||