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77baad0082
A port's direction is read off the cell type, so assigning type_impl = $lut while the $__ICE40_CARRY_WRAPPER ports are still connected makes every following unsetPort consult the wrong type: \B was an input under the wrapper and is not a port of $lut at all, so the teardown takes the output branch and trips `log_assert(w->driverCell_ == this)` in signorm mode (arch/ice40/counter, arch/ice40/bug1598). Disconnect everything under the old type, switch, then connect \A and \Y under the new one. Retiring \O first also leaves that wire undriven, so it comes back as \Y on the same wire rather than behind a freshly interposed alias. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo |
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| .. | ||
| tests | ||
| abc9_model.v | ||
| arith_map.v | ||
| brams.txt | ||
| brams_map.v | ||
| cells_map.v | ||
| cells_sim.v | ||
| CMakeLists.txt | ||
| dsp_map.v | ||
| ff_map.v | ||
| ice40_braminit.cc | ||
| ice40_dsp.cc | ||
| ice40_dsp.pmg | ||
| ice40_opt.cc | ||
| ice40_wrapcarry.cc | ||
| ice40_wrapcarry.pmg | ||
| latches_map.v | ||
| spram.txt | ||
| spram_map.v | ||
| synth_ice40.cc | ||