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yosys/frontends/ast
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José Miguel Sánchez García 5c628387fd Prepend Verilog globals to module AST 
Fixes #4653. Further AST and RTLIL stages seem to be order-sensitive,
and appending globals to the module children list did not work.
2024-10-11 21:25:39 +02:00
..
ast.cc Prepend Verilog globals to module AST 2024-10-11 21:25:39 +02:00
ast.h internal_stats: astnode (sizeof) 2024-09-11 11:34:20 +02:00
ast_binding.cc Generate an RTLIL representation of bind constructs 2021-08-13 17:11:35 -06:00
ast_binding.h Generate an RTLIL representation of bind constructs 2021-08-13 17:11:35 -06:00
dpicall.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
genrtlil.cc Merge pull request #4285 from YosysHQ/typo_fixup 2024-04-25 09:54:48 +12:00
Makefile.inc Generate an RTLIL representation of bind constructs 2021-08-13 17:11:35 -06:00
simplify.cc Added cast to type support (#4284) 2024-09-29 17:03:01 -04:00