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Prepend Verilog globals to module AST

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Fixes #4653. Further AST and RTLIL stages seem to be order-sensitive,
and appending globals to the module children list did not work.
This commit is contained in:
José Miguel Sánchez García 2024-10-11 21:16:57 +02:00
parent 0200a7680a
commit 5c628387fd
1 changed files with 1 additions and 1 deletions
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2
frontends/ast/ast.cc
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@ -1394,7 +1394,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
if (child->type == AST_MODULE || child->type == AST_INTERFACE)
{
for (auto n : design->verilog_globals)
child->children.push_back(n->clone());
child->children.insert(child->children.begin(), n->clone());
// append nodes from previous packages using package-qualified names
for (auto &n : design->verilog_packages) {