José Miguel Sánchez García 5c628387fd Prepend Verilog globals to module AST ... Fixes #4653. Further AST and RTLIL stages seem to be order-sensitive, and appending globals to the module children list did not work.		2024-10-11 21:25:39 +02:00
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aiger	read_aiger: Fix incorrect read of binary Aiger without outputs	2024-04-29 14:06:58 +01:00
aiger2	read_xaiger2: Add help	2024-10-07 14:19:49 +02:00
ast	Prepend Verilog globals to module AST	2024-10-11 21:25:39 +02:00
blif	Issue a warning instead of a syntax error for blif delay constraints	2024-01-23 16:25:16 +00:00
json	fix handling of escaped chars in json backend and frontend	2022-02-18 17:13:09 +01:00
liberty	read_liberty: Optionally import unit delay arcs	2024-09-18 16:17:03 +02:00
rpc	Fitting help messages to 80 character width	2022-08-24 10:40:57 +12:00
rtlil	Remove log	2024-08-21 14:28:42 +01:00
verific	Add left and right bound properties to wire. Add test. Fix printing	2024-09-10 12:52:42 +02:00
verilog	Added cast to type support (#4284)	2024-09-29 17:03:01 -04:00