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aiger
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aiger: add regression test for sliced output segfault
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2025-05-09 16:01:47 +02:00 |
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alumacc
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macc_v2: Add test
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2025-01-27 13:19:26 +01:00 |
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arch
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URAM mapping : Add test for 2048 x 144b
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2025-05-10 14:53:56 +02:00 |
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asicworld
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bind
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blif
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Changed boolopt naming
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2025-01-16 19:36:27 -08:00 |
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bram
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cxxrtl
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Reinstate #4768
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2025-04-08 11:58:05 +12:00 |
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errors
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fmt
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fsm
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functional
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functional tests: run from make tests but not smtlib/rkt tests
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2024-09-04 10:30:08 +01:00 |
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hana
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liberty
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libcache: fix test
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2025-05-09 12:40:38 +02:00 |
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lut
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memfile
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memlib
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fixes for the yosys test
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2025-03-27 17:19:08 -07:00 |
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memories
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rtlil: Adjust internal check for $mem_v2 cells
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2024-11-08 15:18:43 +01:00 |
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opt
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Merge branch 'YosysHQ:main' into main
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2025-05-30 05:00:06 +02:00 |
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opt_share
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peepopt
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Bump yosys to latest
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2025-05-15 14:44:26 -07:00 |
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proc
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Merge pull request #4714 from georgerennie/george/proc_dff_bug_multiple_sigs
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2024-11-20 13:26:32 +01:00 |
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realmath
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rpc
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Remove references to ilang
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2024-11-05 12:36:31 +13:00 |
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sat
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share: Cleanup and additional testing
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2025-04-15 12:34:46 +02:00 |
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select
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design.cc: Fix selections when copying
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2025-04-08 16:35:12 +12:00 |
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share
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silimate
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Merge pull request #82 from donn/splitlarge
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2025-05-15 15:00:45 -07:00 |
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sim
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fstdata.cc: Fix last step
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2025-05-12 13:18:19 +12:00 |
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simple
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Final cleanup
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2025-02-14 10:18:13 -08:00 |
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simple_abc9
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Reinstate #4768
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2025-04-08 11:58:05 +12:00 |
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smv
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Remove references to ilang
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2024-11-05 12:36:31 +13:00 |
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sva
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svinterfaces
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svtypes
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Merge branch 'YosysHQ:main' into main
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2025-06-02 18:47:14 +02:00 |
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techmap
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Merge upstream yosys
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2025-04-21 17:36:24 -07:00 |
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tools
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unit
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rtlil: Add {from,to}_hdl_index methods to Wire
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2025-02-18 17:08:45 +01:00 |
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various
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Bump yosys to latest
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2025-05-15 14:44:26 -07:00 |
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verific
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Revert clocking.ys
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2025-02-13 20:32:17 -08:00 |
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verilog
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Merge pull request #5158 from georgerennie/george/task_inout
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2025-06-04 14:23:08 +01:00 |
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vloghtb
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xprop
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gen-tests-makefile.sh
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Update gen-tests-makefile.sh
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2025-03-27 10:33:51 +13:00 |
