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yosys/techlibs/efinix
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whitequark 550310e264 Harmonize BRAM/LUTRAM descriptions across all of Yosys. 
This commit:
  * renames all remaining instances of "DRAM" (which is ambiguous)
    to "LUTRAM" (which is not), finishing the work started in
    the commit 698ab9be;
  * renames memory rule files to brams.txt/lutrams.txt;
  * adds/renames script labels map_bram/map_lutram;
  * extracts where necessary script labels map_ffram and map_gates;
  * adds where necessary options -nobram/-nolutram.

The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.

Per architecture:
  * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
    :map_lutram, :map_ffram, :map_gates
  * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
  * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
    :map_gates
  * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
    rename -nodram→-nolutram (-nodram still recognized), rename
    :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
2020-01-01 12:30:00 +00:00
..
arith_map.v Fix formating 2019-08-11 17:05:24 +02:00
brams.txt Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
brams_map.v one bit enable signal 2019-08-11 13:59:39 +02:00
cells_map.v Add missing latch mapping 2019-10-04 12:58:11 +02:00
cells_sim.v FF should be initialized to 0 2019-10-04 13:27:10 +02:00
efinix_fixcarry.cc Adding new pass to fix carry chain 2019-08-11 10:17:49 +02:00
efinix_gbuf.cc clock for ram trough gbuf 2019-08-04 12:17:55 +02:00
Makefile.inc Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
synth_efinix.cc Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00