mirror of
https://github.com/YosysHQ/yosys
synced 2026-06-26 18:48:51 +00:00
54d43d85e3
Tiny nit, but the description of `RTLIL::Wire` was using MSB and LSB to refer to the least and most significant *bits* of a wire and not Bytes, which should be referred to using LSb and MSb instead |
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| .. | ||
| _downloads | ||
| _images | ||
| _static | ||
| appendix | ||
| cell | ||
| cmd | ||
| code_examples | ||
| getting_started | ||
| using_yosys | ||
| yosys_internals | ||
| bib.rst | ||
| cell_index.rst | ||
| cmd_ref.rst | ||
| conf.py | ||
| index.rst | ||
| introduction.rst | ||
| literature.bib | ||
| requirements.txt | ||