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yosys/docs/source/yosys_internals
Amelia Dobis 54d43d85e3
[docs] nit: usign the right acronym to refer to the right thing
Tiny nit, but the description of `RTLIL::Wire` was using MSB and LSB to refer to the least and most significant *bits* of a wire and not Bytes, which should be referred to using LSb and MSb instead
2026-06-19 17:30:28 -04:00
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extending_yosys Some more explanations 2026-06-16 10:31:37 +02:00
flow docs: fix verilog frontend internals 2025-08-11 13:34:10 +02:00
formats [docs] nit: usign the right acronym to refer to the right thing 2026-06-19 17:30:28 -04:00
hashing.rst pyosys: rewrite using pybind11 2025-10-03 11:54:44 +03:00
index.rst Update documentation and few more defines 2026-05-13 11:24:45 +02:00
techmap.rst Docs: Reflow line length 2024-10-15 07:23:45 +13:00