This website requires JavaScript.
Explore
Help
Register
Sign in
mirrors
/
yosys
Watch
3
Star
0
Fork
You've already forked yosys
0
mirror of
https://github.com/YosysHQ/yosys
synced
2025-10-25 00:44:37 +00:00
Code
Activity
540623a513
yosys
/
passes
History
Emil J. Tywoniak
8a873a7724
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-07-10 21:15:50 +02:00
..
cmds
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-07-10 21:15:50 +02:00
equiv
mark all hash_into methods nodiscard
2025-01-14 12:39:15 +01:00
fsm
io: refactor string and file work into new unit
2025-03-19 13:43:42 +01:00
hierarchy
don't warn for every blackbox from verific
2025-06-06 15:37:42 +02:00
memory
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-07-10 21:15:50 +02:00
opt
opt_dff: don't emit cells until all have been visited to prevent UAF
2025-06-06 23:46:07 +01:00
pmgen
io: refactor string and file work into new unit
2025-03-19 13:43:42 +01:00
proc
Proc: Use selections consistently
2025-05-31 12:04:42 +12:00
sat
Merge pull request
#5116
from YosysHQ/krys/update_fst
2025-05-16 09:22:52 +12:00
techmap
Merge pull request
#5190
from YosysHQ/emil/dfflibmap-fix-negated-next_state
2025-07-10 19:50:02 +02:00
tests
macc: Rename 'ports' to 'terms' throughout codebase
2025-03-18 13:25:10 +01:00