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dynamic_part_select
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Adding latch tests for shift&mask AST dynamic part-select enhancements
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2020-06-09 15:17:01 -05:00 |
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.gitignore
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Add plugin.so.dSYM to .gitignore
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2021-01-18 11:13:21 -07:00 |
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abc9.v
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abc9.ys
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abc9: uniquify blackboxes like whiteboxes (#2695)
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2021-03-29 22:02:06 -07:00 |
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async.sh
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async.v
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attrib05_port_conn.v
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attrib05_port_conn.ys
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attrib07_func_call.v
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attrib07_func_call.ys
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
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autoname.ys
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blackbox_wb.ys
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blackbox: Include whiteboxed modules
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2021-03-17 13:58:04 +00:00 |
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bug1496.ys
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bug1531.ys
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Add testcase
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2019-12-11 16:52:37 -08:00 |
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bug1614.ys
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bug1710.ys
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bug1745.ys
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Add regression tests for new handling of comments in constants
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2020-03-14 11:41:09 +01:00 |
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bug1781.ys
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bug1876.ys
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tests: add testcases from #1876
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2020-04-14 12:39:10 -07:00 |
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bug2014.ys
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chparam.sh
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const_arg_loop.sv
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verilog: fix sizing of constant args for tasks/functions
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2021-02-21 15:44:43 -05:00 |
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const_arg_loop.ys
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verilog: fix sizing of constant args for tasks/functions
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2021-02-21 15:44:43 -05:00 |
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const_func.sv
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verilog: fix sizing of constant args for tasks/functions
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2021-02-21 15:44:43 -05:00 |
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const_func.ys
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verilog: fix sizing of constant args for tasks/functions
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2021-02-21 15:44:43 -05:00 |
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const_func_block_var.v
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const_func_block_var.ys
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constcomment.ys
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constmsk_test.v
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Added tests/various/constmsk_test.ys
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2014-09-04 15:07:30 +02:00 |
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constmsk_test.ys
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constmsk_testmap.v
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countbits.sv
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Add tests for $countbits
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2021-02-26 12:28:58 -05:00 |
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countbits.ys
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Add tests for $countbits
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2021-02-26 12:28:58 -05:00 |
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deminout_unused.ys
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design.ys
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design: add test
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2020-04-16 12:48:40 -07:00 |
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design1.ys
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design: add test
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2020-04-16 12:48:40 -07:00 |
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design2.ys
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dynamic_part_select.ys
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elab_sys_tasks.sv
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elab_sys_tasks.ys
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equiv_opt_multiclock.ys
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equiv_opt_undef.ys
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exec.ys
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fib.v
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verilog: improved support for recursive functions
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2020-12-31 18:33:59 -07:00 |
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fib.ys
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verilog: improved support for recursive functions
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2020-12-31 18:33:59 -07:00 |
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fib_tern.v
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verilog: support recursive functions using ternary expressions
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2021-02-12 14:43:42 -05:00 |
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fib_tern.ys
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verilog: support recursive functions using ternary expressions
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2021-02-12 14:43:42 -05:00 |
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func_port_implied_dir.sv
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sv: complete support for implied task/function port directions
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2020-12-31 16:17:13 -07:00 |
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func_port_implied_dir.ys
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sv: complete support for implied task/function port directions
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2020-12-31 16:17:13 -07:00 |
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gen_if_null.v
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verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
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gen_if_null.ys
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verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
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global_scope.ys
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gzip_verilog.v.gz
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Add support for reading gzip'd input files
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2019-07-26 10:23:58 +01:00 |
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gzip_verilog.ys
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help.ys
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hierarchy.sh
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hierarchy_defer.ys
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Expand test with `hierarchy' without -auto-top
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2019-09-03 12:17:26 -07:00 |
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hierarchy_param.ys
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ice40_mince_abc9.ys
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integer_range_bad_syntax.ys
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integer_real_bad_syntax.ys
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logger_error.ys
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logger_nowarning.ys
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logger_warn.ys
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logger_warning.ys
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logic_param_simple.ys
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mem2reg.ys
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memory_word_as_index.data
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Fix elaboration of whole memory words used as indices
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2020-12-26 21:47:38 -07:00 |
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memory_word_as_index.v
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Fix elaboration of whole memory words used as indices
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2020-12-26 21:47:38 -07:00 |
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memory_word_as_index.ys
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Fix elaboration of whole memory words used as indices
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2020-12-26 21:47:38 -07:00 |
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muxcover.ys
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muxpack.v
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More deadname stuff
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2021-06-09 12:40:33 +02:00 |
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muxpack.ys
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More deadname stuff
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2021-06-09 12:40:33 +02:00 |
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peepopt.ys
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plugin.cc
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plugin.sh
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pmgen_reduce.ys
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pmux2shiftx.v
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Cleanup tests
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2020-02-27 10:17:29 -08:00 |
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pmux2shiftx.ys
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port_sign_extend.v
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genrtlil: fix signed port connection codegen failures
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2021-02-05 19:51:30 -05:00 |
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port_sign_extend.ys
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genrtlil: fix signed port connection codegen failures
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2021-02-05 19:51:30 -05:00 |
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primitives.ys
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printattr.ys
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rand_const.sv
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Allow combination of rand and const modifiers
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2021-01-21 08:42:05 -07:00 |
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rand_const.ys
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Allow combination of rand and const modifiers
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2021-01-21 08:42:05 -07:00 |
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reg_wire_error.sv
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reg_wire_error.ys
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run-test.sh
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tests: Centralize test collection and Makefile generation
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2020-09-21 15:07:02 +02:00 |
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scratchpad.ys
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script.ys
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sformatf.ys
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ast: Add support for $sformatf system function
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2020-01-19 21:20:17 +00:00 |
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shregmap.v
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tests: fix some test warnings
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2020-05-25 10:07:58 -07:00 |
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shregmap.ys
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Remove Xilinx test
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2019-08-22 16:18:07 -07:00 |
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signed.ys
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signext.ys
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Extend sign extension tests
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2019-06-20 12:43:59 -07:00 |
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sim_const.ys
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specify.v
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specify.ys
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src.ys
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submod.ys
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Add a quick testcase for unknown modules as inout
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2019-12-09 13:14:46 -08:00 |
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submod_extract.ys
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sv_defines.ys
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sv_defines_dup.ys
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sv_defines_mismatch.ys
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sv_defines_too_few.ys
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
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sv_implicit_ports.sh
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svalways.sh
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wreduce.ys
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write_gzip.ys
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xaiger.ys
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