mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-09 17:31:59 +00:00
4a99aa09cb
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy). Drop the unused defines from the synth pass. Remove comments from the lutram files referencing xilinx.
41 lines
507 B
Text
41 lines
507 B
Text
# Single-port RAMs.
|
|
|
|
ram distributed $__ANALOGDEVICES_LUTRAM_SP_ {
|
|
option "ABITS" 5 {
|
|
cost 1;
|
|
abits 5;
|
|
width 1;
|
|
}
|
|
option "ABITS" 6 {
|
|
cost 2;
|
|
abits 6;
|
|
width 1;
|
|
}
|
|
init no_undef;
|
|
prune_rom;
|
|
port arsw "RW" {
|
|
clock anyedge;
|
|
}
|
|
}
|
|
|
|
# Dual-port RAMs.
|
|
|
|
ram distributed $__ANALOGDEVICES_LUTRAM_DP_ {
|
|
option "ABITS" 5 {
|
|
cost 2;
|
|
abits 5;
|
|
width 1;
|
|
}
|
|
option "ABITS" 6 {
|
|
cost 4;
|
|
abits 6;
|
|
width 1;
|
|
}
|
|
init no_undef;
|
|
prune_rom;
|
|
port arsw "RW" {
|
|
clock anyedge;
|
|
}
|
|
port ar "R" {
|
|
}
|
|
}
|