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analogdevices: (some) Native BRAM
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy). Drop the unused defines from the synth pass. Remove comments from the lutram files referencing xilinx.
This commit is contained in:
Krystine Sherwin
parent
e8127ff5f3
commit
4a99aa09cb
6 changed files with 116 additions and 875 deletions
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@ -1,165 +1,39 @@
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# Block RAMs for Virtex 4+.
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# The corresponding mapping files are:
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# - brams_xc6v_map.v: Virtex 6, Series 7
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# Simple Dual Port
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# Supported:
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# SDP_4096x05
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# SDP_2048x10
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# SDP_1024x40
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# Ignored:
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# SDP_2048x09
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ram block $__ANALOGDEVICES_BLOCKRAM_TDP_ {
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byte 9;
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ifdef HAS_SIZE_36 {
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option "MODE" "HALF" {
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abits 14;
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widths 1 2 4 9 18 per_port;
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cost 129;
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}
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option "MODE" "FULL" {
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abits 15;
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widths 1 2 4 9 18 36 per_port;
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cost 257;
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}
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ifdef HAS_CASCADE {
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option "MODE" "CASCADE" {
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abits 16;
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# hack to enforce same INIT layout as in the other modes
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widths 1 2 4 9 per_port;
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cost 513;
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}
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}
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} else {
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option "MODE" "FULL" {
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abits 14;
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widths 1 2 4 9 18 36 per_port;
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cost 129;
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}
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ifdef HAS_CASCADE {
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option "MODE" "CASCADE" {
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abits 15;
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widths 1 2 4 9 per_port;
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cost 257;
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}
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}
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ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ {
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option "ENABLE_WIDTH" "BIT" {
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abits 12;
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widths 5 10 global;
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byte 1;
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cost 1;
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}
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init any;
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port srsw "A" "B" {
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option "MODE" "HALF" {
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width mix;
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}
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option "MODE" "FULL" {
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width mix;
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}
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option "MODE" "CASCADE" {
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width mix 1;
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}
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ifdef HAS_ADDRCE {
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# TODO
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# addrce;
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}
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# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.
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ifdef HAS_CONFLICT_BUG {
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option "HAS_RDFIRST" 1 {
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clock posedge "C";
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}
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option "HAS_RDFIRST" 0 {
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clock posedge;
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}
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} else {
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clock posedge;
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}
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option "ENABLE_WIDTH" "BYTE" {
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abits 10;
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width 40;
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byte 8;
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cost 4;
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}
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# Unclear if/how RBRAM is initialized, default SIM_INIT_BEHAVIOUR is UNINITIALIZED
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init none;
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port sr "R" {
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clock anyedge;
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clken;
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}
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port sw "W" {
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clock anyedge;
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clken;
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rdsrst any gated_clken;
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rdinit any;
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portoption "WRITE_MODE" "NO_CHANGE" {
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rdwr no_change;
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option "MODE" "CASCADE" {
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forbid;
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}
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}
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portoption "WRITE_MODE" "WRITE_FIRST" {
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ifdef HAS_SIZE_36 {
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rdwr new;
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} else {
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rdwr new_only;
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}
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}
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ifdef HAS_CONFLICT_BUG {
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option "HAS_RDFIRST" 1 {
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portoption "WRITE_MODE" "READ_FIRST" {
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rdwr old;
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wrtrans all old;
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}
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}
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} else {
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portoption "WRITE_MODE" "READ_FIRST" {
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rdwr old;
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wrtrans all old;
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}
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}
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optional_rw;
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}
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}
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ifdef HAS_SIZE_36 {
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ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ {
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byte 9;
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option "MODE" "HALF" {
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abits 14;
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widths 1 2 4 9 18 36 per_port;
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cost 129;
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}
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option "MODE" "FULL" {
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abits 15;
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widths 1 2 4 9 18 36 72 per_port;
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cost 257;
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}
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init any;
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port sw "W" {
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ifndef HAS_MIXWIDTH_SDP {
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option "MODE" "HALF" width 36;
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option "MODE" "FULL" width 72;
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}
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ifdef HAS_ADDRCE {
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# TODO
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# addrce;
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}
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# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.
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ifdef HAS_CONFLICT_BUG {
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option "WRITE_MODE" "READ_FIRST" {
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clock posedge "C";
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}
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option "WRITE_MODE" "WRITE_FIRST" {
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clock posedge;
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}
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} else {
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clock posedge;
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}
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clken;
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option "WRITE_MODE" "READ_FIRST" {
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wrtrans all old;
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}
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optional;
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}
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port sr "R" {
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ifndef HAS_MIXWIDTH_SDP {
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option "MODE" "HALF" width 36;
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option "MODE" "FULL" width 72;
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}
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ifdef HAS_ADDRCE {
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# TODO
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# addrce;
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}
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# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.
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ifdef HAS_CONFLICT_BUG {
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option "WRITE_MODE" "READ_FIRST" {
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clock posedge "C";
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}
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option "WRITE_MODE" "WRITE_FIRST" {
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clock posedge;
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}
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} else {
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clock posedge;
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}
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clken;
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rdsrst any gated_clken;
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rdinit any;
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optional;
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}
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}
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}
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# Single Port
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# SP_1024x20
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# Dual Single Port
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# SP2_1024x09
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# SP2_2048x05
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@ -1,284 +1,64 @@
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module $__ANALOGDEVICES_BLOCKRAM_TDP_ (...);
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parameter INIT = 0;
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parameter OPTION_MODE = "FULL";
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parameter OPTION_HAS_RDFIRST = 0;
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parameter PORT_A_RD_WIDTH = 1;
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parameter PORT_A_WR_WIDTH = 1;
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parameter PORT_A_WR_EN_WIDTH = 1;
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parameter PORT_A_RD_USED = 1;
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parameter PORT_A_WR_USED = 1;
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parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE";
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parameter PORT_A_RD_INIT_VALUE = 0;
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parameter PORT_A_RD_SRST_VALUE = 1;
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parameter PORT_B_RD_WIDTH = 1;
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parameter PORT_B_WR_WIDTH = 1;
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parameter PORT_B_WR_EN_WIDTH = 1;
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parameter PORT_B_RD_USED = 0;
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parameter PORT_B_WR_USED = 0;
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parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE";
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parameter PORT_B_RD_INIT_VALUE = 0;
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parameter PORT_B_RD_SRST_VALUE = 0;
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input CLK_C;
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input [15:0] PORT_A_ADDR;
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input [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA;
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input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
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output [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA;
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input PORT_A_RD_SRST;
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input [15:0] PORT_B_ADDR;
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input [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA;
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input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
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output [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA;
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input PORT_B_RD_SRST;
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`include "brams_defs.vh"
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`define PARAMS_COMMON \
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.WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \
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.WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \
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.READ_WIDTH_A(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), \
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.READ_WIDTH_B(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), \
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.WRITE_WIDTH_A(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), \
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.WRITE_WIDTH_B(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), \
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.DOA_REG(0), \
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.DOB_REG(0), \
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.INIT_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_INIT_VALUE)), \
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.INIT_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_INIT_VALUE)), \
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.SRVAL_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_SRST_VALUE)), \
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.SRVAL_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_SRST_VALUE)), \
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.RAM_MODE("TDP"),
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`define PORTS_COMMON \
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.DOADO(DO_A), \
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.DOPADOP(DOP_A), \
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.DIADI(DI_A), \
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.DIPADIP(DIP_A), \
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.DOBDO(DO_B), \
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.DOPBDOP(DOP_B), \
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.DIBDI(DI_B), \
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.DIPBDIP(DIP_B), \
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.CLKARDCLK(PORT_A_CLK), \
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.CLKBWRCLK(PORT_B_CLK), \
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.ENARDEN(PORT_A_CLK_EN), \
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.ENBWREN(PORT_B_CLK_EN), \
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.REGCEAREGCE(1'b0), \
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.REGCEB(1'b0), \
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.RSTRAMARSTRAM(PORT_A_RD_SRST), \
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.RSTRAMB(PORT_B_RD_SRST), \
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.RSTREGARSTREG(1'b0), \
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.RSTREGB(1'b0), \
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.WEA(WE_A), \
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.WEBWE(WE_B),
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`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA)
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`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA)
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`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA)
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`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA)
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wire [3:0] WE_A = {4{PORT_A_WR_EN}};
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wire [3:0] WE_B = {4{PORT_B_WR_EN}};
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generate
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if (OPTION_MODE == "HALF") begin
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RAMB18E1 #(
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`PARAMS_INIT_18
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`PARAMS_INITP_18
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`PARAMS_COMMON
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) _TECHMAP_REPLACE_ (
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`PORTS_COMMON
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.ADDRARDADDR(PORT_A_ADDR[13:0]),
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.ADDRBWRADDR(PORT_B_ADDR[13:0]),
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);
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end else if (OPTION_MODE == "FULL") begin
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RAMB36E1 #(
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`PARAMS_INIT_36
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`PARAMS_INITP_36
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`PARAMS_COMMON
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.RAM_EXTENSION_A("NONE"),
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.RAM_EXTENSION_B("NONE"),
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) _TECHMAP_REPLACE_ (
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`PORTS_COMMON
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.ADDRARDADDR({1'b1, PORT_A_ADDR[14:0]}),
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.ADDRBWRADDR({1'b1, PORT_B_ADDR[14:0]}),
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);
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end else begin
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wire CAS_A, CAS_B;
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RAMB36E1 #(
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`PARAMS_INIT_36
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`PARAMS_COMMON
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.RAM_EXTENSION_A("LOWER"),
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.RAM_EXTENSION_B("LOWER"),
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) lower (
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.DIADI(DI_A),
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.DIBDI(DI_B),
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.CLKARDCLK(PORT_A_CLK),
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.CLKBWRCLK(PORT_B_CLK),
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.ENARDEN(PORT_A_CLK_EN),
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.ENBWREN(PORT_B_CLK_EN),
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.REGCEAREGCE(1'b0),
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.REGCEB(1'b0),
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.RSTRAMARSTRAM(PORT_A_RD_SRST),
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.RSTRAMB(PORT_B_RD_SRST),
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.RSTREGARSTREG(1'b0),
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.RSTREGB(1'b0),
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.WEA(WE_A),
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.WEBWE(WE_B),
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.ADDRARDADDR(PORT_A_ADDR),
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.ADDRBWRADDR(PORT_B_ADDR),
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.CASCADEOUTA(CAS_A),
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.CASCADEOUTB(CAS_B),
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);
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RAMB36E1 #(
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`PARAMS_INIT_36_U
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`PARAMS_COMMON
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.RAM_EXTENSION_A("UPPER"),
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.RAM_EXTENSION_B("UPPER"),
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) upper (
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.DOADO(DO_A),
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.DIADI(DI_A),
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.DOBDO(DO_B),
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.DIBDI(DI_B),
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.CLKARDCLK(PORT_A_CLK),
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.CLKBWRCLK(PORT_B_CLK),
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.ENARDEN(PORT_A_CLK_EN),
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.ENBWREN(PORT_B_CLK_EN),
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.REGCEAREGCE(1'b0),
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.REGCEB(1'b0),
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.RSTRAMARSTRAM(PORT_A_RD_SRST),
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.RSTRAMB(PORT_B_RD_SRST),
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.RSTREGARSTREG(1'b0),
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.RSTREGB(1'b0),
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.WEA(WE_A),
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.WEBWE(WE_B),
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.ADDRARDADDR(PORT_A_ADDR),
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.ADDRBWRADDR(PORT_B_ADDR),
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.CASCADEINA(CAS_A),
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.CASCADEINB(CAS_B),
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);
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end
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endgenerate
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endmodule
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module $__ANALOGDEVICES_BLOCKRAM_SDP_ (...);
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parameter INIT = 0;
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parameter OPTION_MODE = "FULL";
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parameter OPTION_WRITE_MODE = "READ_FIRST";
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parameter OPTION_ENABLE_WIDTH = "BIT";
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parameter WIDTH = 40;
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parameter PORT_W_WIDTH = 1;
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parameter PORT_W_WR_EN_WIDTH = 1;
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parameter PORT_W_USED = 1;
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parameter PORT_W_WR_EN_WIDTH = 5;
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parameter PORT_W_CLK_POL = 1;
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parameter PORT_R_WIDTH = 1;
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parameter PORT_R_USED = 0;
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parameter PORT_R_RD_INIT_VALUE = 0;
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parameter PORT_R_RD_SRST_VALUE = 0;
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input CLK_C;
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parameter PORT_R_CLK_POL = 1;
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input PORT_W_CLK;
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input PORT_W_CLK_EN;
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input [15:0] PORT_W_ADDR;
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input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
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input [11:0] PORT_W_ADDR;
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input [WIDTH-1:0] PORT_W_WR_DATA;
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input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
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input PORT_R_CLK;
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input PORT_R_CLK_EN;
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input [15:0] PORT_R_ADDR;
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output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
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input PORT_R_RD_SRST;
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input [11:0] PORT_R_ADDR;
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output [WIDTH-1:0] PORT_R_RD_DATA;
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`include "brams_defs.vh"
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`define PARAMS_COMMON \
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.WRITE_MODE_A(OPTION_WRITE_MODE), \
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.WRITE_MODE_B(OPTION_WRITE_MODE), \
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.READ_WIDTH_A(PORT_R_USED ? PORT_R_WIDTH : 0), \
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.READ_WIDTH_B(0), \
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.WRITE_WIDTH_A(0), \
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.WRITE_WIDTH_B(PORT_W_USED ? PORT_W_WIDTH : 0), \
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.DOA_REG(0), \
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.DOB_REG(0), \
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.RAM_MODE("SDP"),
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`define PORTS_COMMON \
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.CLKBWRCLK(PORT_W_CLK), \
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.CLKARDCLK(PORT_R_CLK), \
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.ENBWREN(PORT_W_CLK_EN), \
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.ENARDEN(PORT_R_CLK_EN), \
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.REGCEAREGCE(1'b0), \
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.REGCEB(1'b0), \
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.RSTRAMARSTRAM(PORT_R_RD_SRST), \
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.RSTRAMB(1'b0), \
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.RSTREGARSTREG(1'b0), \
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.RSTREGB(1'b0), \
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.WEA(0), \
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.WEBWE(PORT_W_WR_EN),
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`MAKE_DI(DI, DIP, PORT_W_WR_DATA)
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`MAKE_DO(DO, DOP, PORT_R_RD_DATA)
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generate
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if (OPTION_MODE == "HALF") begin
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RAMB18E1 #(
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`PARAMS_INIT_18
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`PARAMS_INITP_18
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`PARAMS_COMMON
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.INIT_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)),
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.INIT_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[35:18]) : 0),
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.SRVAL_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)),
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.SRVAL_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[35:18]) : 0),
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) _TECHMAP_REPLACE_ (
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`PORTS_COMMON
|
||||
.ADDRARDADDR(PORT_R_ADDR[13:0]),
|
||||
.ADDRBWRADDR(PORT_W_ADDR[13:0]),
|
||||
.DOADO(DO[15:0]),
|
||||
.DOBDO(DO[31:16]),
|
||||
.DOPADOP(DOP[1:0]),
|
||||
.DOPBDOP(DOP[3:2]),
|
||||
.DIADI(DI[15:0]),
|
||||
.DIBDI(PORT_W_WIDTH == 36 ? DI[31:16] : DI[15:0]),
|
||||
.DIPADIP(DIP[1:0]),
|
||||
.DIPBDIP(PORT_W_WIDTH == 36 ? DIP[3:2] : DIP[1:0]),
|
||||
);
|
||||
end else if (OPTION_MODE == "FULL") begin
|
||||
RAMB36E1 #(
|
||||
`PARAMS_INIT_36
|
||||
`PARAMS_INITP_36
|
||||
`PARAMS_COMMON
|
||||
.INIT_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)),
|
||||
.INIT_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[71:36]) : 0),
|
||||
.SRVAL_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)),
|
||||
.SRVAL_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[71:36]) : 0),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_COMMON
|
||||
.ADDRARDADDR({1'b1, PORT_R_ADDR}),
|
||||
.ADDRBWRADDR({1'b1, PORT_W_ADDR}),
|
||||
.DOADO(DO[31:0]),
|
||||
.DOBDO(DO[63:32]),
|
||||
.DOPADOP(DOP[3:0]),
|
||||
.DOPBDOP(DOP[7:4]),
|
||||
.DIADI(DI[31:0]),
|
||||
.DIBDI(PORT_W_WIDTH == 72 ? DI[63:32] : DI[31:0]),
|
||||
.DIPADIP(DIP[3:0]),
|
||||
.DIPBDIP(PORT_W_WIDTH == 71 ? DIP[7:4] : DIP[3:0]),
|
||||
);
|
||||
end
|
||||
|
||||
endgenerate
|
||||
RBRAM
|
||||
#(
|
||||
.TARGET_NODE("T40LP_Gen2.4"),
|
||||
.BRAM_MODE(
|
||||
WIDTH == 5 ? "SDP_4096x05" :
|
||||
WIDTH == 10 ? "SDP_2048x10" : "SDP_1024x40"
|
||||
),
|
||||
.QA_REG(0),
|
||||
.QB_REG(0),
|
||||
.CLKA_INV(!PORT_W_CLK_POL),
|
||||
.CLKB_INV(!PORT_R_CLK_POL),
|
||||
.DATA_WIDTH(WIDTH),
|
||||
.ADDR_WIDTH(
|
||||
WIDTH == 5 ? 12 :
|
||||
WIDTH == 10 ? 11 : 10
|
||||
),
|
||||
.WE_WIDTH(OPTION_ENABLE_WIDTH == "BIT" ? WIDTH : PORT_W_WR_EN_WIDTH),
|
||||
.PERR_WIDTH(1),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
// .QA(0),
|
||||
.DA(PORT_W_WR_DATA),
|
||||
.CEA(PORT_W_CLK_EN),
|
||||
.WEA(PORT_W_WR_EN),
|
||||
.AA(
|
||||
WIDTH == 5 ? PORT_W_ADDR :
|
||||
WIDTH == 10 ? PORT_W_ADDR[11:1] : PORT_W_ADDR[11:2]
|
||||
),
|
||||
.CLKA(PORT_W_CLK),
|
||||
.QB(PORT_R_RD_DATA),
|
||||
// .DB(0),
|
||||
.CEB(PORT_R_CLK_EN),
|
||||
// .WEB(0),
|
||||
.AB(
|
||||
WIDTH == 5 ? PORT_R_ADDR :
|
||||
WIDTH == 10 ? PORT_R_ADDR[11:1] : PORT_R_ADDR[11:2]
|
||||
),
|
||||
.CLKB(PORT_R_CLK),
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -2423,444 +2423,42 @@ endmodule
|
|||
|
||||
// Block RAM
|
||||
|
||||
module RAMB18E1 (
|
||||
module RBRAM #(
|
||||
parameter TARGET_NODE = "T40LP_Gen2.4",
|
||||
parameter BRAM_MODE = "SDP_1024x40",
|
||||
parameter QA_REG = 0,
|
||||
parameter QB_REG = 0,
|
||||
parameter CLKA_INV = 0,
|
||||
parameter CLKB_INV = 0,
|
||||
parameter DATA_WIDTH = 40,
|
||||
parameter ADDR_WIDTH = 12,
|
||||
parameter WE_WIDTH = 10,
|
||||
parameter PERR_WIDTH = 4,
|
||||
) (
|
||||
output [DATA_WIDTH-1:0] QA,
|
||||
input [DATA_WIDTH-1:0] DA,
|
||||
input CEA,
|
||||
input [WE_WIDTH-1:0] WEA,
|
||||
input [ADDR_WIDTH-1:0] AA,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
|
||||
input CLKARDCLK,
|
||||
(* invertible_pin = "CLKA_INV" *)
|
||||
input CLKA,
|
||||
output [DATA_WIDTH-1:0] QB,
|
||||
input [DATA_WIDTH-1:0] DB,
|
||||
input CEB,
|
||||
input [WE_WIDTH-1:0] WEB,
|
||||
input [ADDR_WIDTH-1:0] AB,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
|
||||
input CLKBWRCLK,
|
||||
(* invertible_pin = "IS_ENARDEN_INVERTED" *)
|
||||
input ENARDEN,
|
||||
(* invertible_pin = "IS_ENBWREN_INVERTED" *)
|
||||
input ENBWREN,
|
||||
input REGCEAREGCE,
|
||||
input REGCEB,
|
||||
(* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
|
||||
input RSTRAMARSTRAM,
|
||||
(* invertible_pin = "IS_RSTRAMB_INVERTED" *)
|
||||
input RSTRAMB,
|
||||
(* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
|
||||
input RSTREGARSTREG,
|
||||
(* invertible_pin = "IS_RSTREGB_INVERTED" *)
|
||||
input RSTREGB,
|
||||
input [13:0] ADDRARDADDR,
|
||||
input [13:0] ADDRBWRADDR,
|
||||
input [15:0] DIADI,
|
||||
input [15:0] DIBDI,
|
||||
input [1:0] DIPADIP,
|
||||
input [1:0] DIPBDIP,
|
||||
input [1:0] WEA,
|
||||
input [3:0] WEBWE,
|
||||
output [15:0] DOADO,
|
||||
output [15:0] DOBDO,
|
||||
output [1:0] DOPADOP,
|
||||
output [1:0] DOPBDOP
|
||||
(* invertible_pin = "CLKB_INV" *)
|
||||
input CLKB,
|
||||
output reg [PERR_WIDTH-1:0] PERRA,
|
||||
output reg [PERR_WIDTH-1:0] PERRB,
|
||||
output SBEA,
|
||||
output SBEB,
|
||||
output MBEA,
|
||||
output MBEB,
|
||||
input SLP,
|
||||
input PD,
|
||||
);
|
||||
parameter integer DOA_REG = 0;
|
||||
parameter integer DOB_REG = 0;
|
||||
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_A = 18'h0;
|
||||
parameter INIT_B = 18'h0;
|
||||
parameter INIT_FILE = "NONE";
|
||||
parameter RAM_MODE = "TDP";
|
||||
parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
|
||||
parameter integer READ_WIDTH_A = 0;
|
||||
parameter integer READ_WIDTH_B = 0;
|
||||
parameter RSTREG_PRIORITY_A = "RSTREG";
|
||||
parameter RSTREG_PRIORITY_B = "RSTREG";
|
||||
parameter SIM_COLLISION_CHECK = "ALL";
|
||||
parameter SIM_DEVICE = "VIRTEX6";
|
||||
parameter SRVAL_A = 18'h0;
|
||||
parameter SRVAL_B = 18'h0;
|
||||
parameter WRITE_MODE_A = "WRITE_FIRST";
|
||||
parameter WRITE_MODE_B = "WRITE_FIRST";
|
||||
parameter integer WRITE_WIDTH_A = 0;
|
||||
parameter integer WRITE_WIDTH_B = 0;
|
||||
parameter IS_CLKARDCLK_INVERTED = 1'b0;
|
||||
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
|
||||
parameter IS_ENARDEN_INVERTED = 1'b0;
|
||||
parameter IS_ENBWREN_INVERTED = 1'b0;
|
||||
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
|
||||
parameter IS_RSTRAMB_INVERTED = 1'b0;
|
||||
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
|
||||
parameter IS_RSTREGB_INVERTED = 1'b0;
|
||||
|
||||
specify
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13
|
||||
$setup(ADDRARDADDR, posedge CLKARDCLK, 566);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17
|
||||
$setup(ADDRBWRADDR, posedge CLKBWRCLK, 566);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19
|
||||
$setup(WEA, posedge CLKARDCLK, 532);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21
|
||||
$setup(WEBWE, posedge CLKBWRCLK, 532);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L29
|
||||
$setup(REGCEAREGCE, posedge CLKARDCLK, 360);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L31
|
||||
$setup(RSTREGARSTREG, posedge CLKARDCLK, 342);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L49
|
||||
$setup(REGCEB, posedge CLKBWRCLK, 360);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L59
|
||||
$setup(RSTREGB, posedge CLKBWRCLK, 342);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123
|
||||
$setup(DIADI, posedge CLKARDCLK, 737);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133
|
||||
$setup(DIBDI, posedge CLKBWRCLK, 737);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125
|
||||
$setup(DIPADIP, posedge CLKARDCLK, 737);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135
|
||||
$setup(DIPBDIP, posedge CLKBWRCLK, 737);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143
|
||||
if (&DOA_REG) (posedge CLKARDCLK => (DOADO : 16'bx)) = 2454;
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144
|
||||
if (&DOA_REG) (posedge CLKARDCLK => (DOPADOP : 2'bx)) = 2454;
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L153
|
||||
if (|DOA_REG) (posedge CLKARDCLK => (DOADO : 16'bx)) = 882;
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L154
|
||||
if (|DOA_REG) (posedge CLKARDCLK => (DOPADOP : 2'bx)) = 882;
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163
|
||||
if (&DOB_REG) (posedge CLKBWRCLK => (DOBDO : 16'bx)) = 2454;
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164
|
||||
if (&DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 2'bx)) = 2454;
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L173
|
||||
if (|DOB_REG) (posedge CLKBWRCLK => (DOBDO : 16'bx)) = 882;
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L174
|
||||
if (|DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 2'bx)) = 882;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
module RAMB36E1 (
|
||||
output CASCADEOUTA,
|
||||
output CASCADEOUTB,
|
||||
output [31:0] DOADO,
|
||||
output [31:0] DOBDO,
|
||||
output [3:0] DOPADOP,
|
||||
output [3:0] DOPBDOP,
|
||||
output [7:0] ECCPARITY,
|
||||
output [8:0] RDADDRECC,
|
||||
output SBITERR,
|
||||
output DBITERR,
|
||||
(* invertible_pin = "IS_ENARDEN_INVERTED" *)
|
||||
input ENARDEN,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
|
||||
input CLKARDCLK,
|
||||
(* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
|
||||
input RSTRAMARSTRAM,
|
||||
(* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
|
||||
input RSTREGARSTREG,
|
||||
input CASCADEINA,
|
||||
input REGCEAREGCE,
|
||||
(* invertible_pin = "IS_ENBWREN_INVERTED" *)
|
||||
input ENBWREN,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
|
||||
input CLKBWRCLK,
|
||||
(* invertible_pin = "IS_RSTRAMB_INVERTED" *)
|
||||
input RSTRAMB,
|
||||
(* invertible_pin = "IS_RSTREGB_INVERTED" *)
|
||||
input RSTREGB,
|
||||
input CASCADEINB,
|
||||
input REGCEB,
|
||||
input INJECTDBITERR,
|
||||
input INJECTSBITERR,
|
||||
input [15:0] ADDRARDADDR,
|
||||
input [15:0] ADDRBWRADDR,
|
||||
input [31:0] DIADI,
|
||||
input [31:0] DIBDI,
|
||||
input [3:0] DIPADIP,
|
||||
input [3:0] DIPBDIP,
|
||||
input [3:0] WEA,
|
||||
input [7:0] WEBWE
|
||||
);
|
||||
parameter integer DOA_REG = 0;
|
||||
parameter integer DOB_REG = 0;
|
||||
parameter EN_ECC_READ = "FALSE";
|
||||
parameter EN_ECC_WRITE = "FALSE";
|
||||
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_A = 36'h0;
|
||||
parameter INIT_B = 36'h0;
|
||||
parameter INIT_FILE = "NONE";
|
||||
parameter RAM_EXTENSION_A = "NONE";
|
||||
parameter RAM_EXTENSION_B = "NONE";
|
||||
parameter RAM_MODE = "TDP";
|
||||
parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
|
||||
parameter integer READ_WIDTH_A = 0;
|
||||
parameter integer READ_WIDTH_B = 0;
|
||||
parameter RSTREG_PRIORITY_A = "RSTREG";
|
||||
parameter RSTREG_PRIORITY_B = "RSTREG";
|
||||
parameter SIM_COLLISION_CHECK = "ALL";
|
||||
parameter SIM_DEVICE = "VIRTEX6";
|
||||
parameter SRVAL_A = 36'h0;
|
||||
parameter SRVAL_B = 36'h0;
|
||||
parameter WRITE_MODE_A = "WRITE_FIRST";
|
||||
parameter WRITE_MODE_B = "WRITE_FIRST";
|
||||
parameter integer WRITE_WIDTH_A = 0;
|
||||
parameter integer WRITE_WIDTH_B = 0;
|
||||
parameter IS_CLKARDCLK_INVERTED = 1'b0;
|
||||
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
|
||||
parameter IS_ENARDEN_INVERTED = 1'b0;
|
||||
parameter IS_ENBWREN_INVERTED = 1'b0;
|
||||
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
|
||||
parameter IS_RSTRAMB_INVERTED = 1'b0;
|
||||
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
|
||||
parameter IS_RSTREGB_INVERTED = 1'b0;
|
||||
|
||||
specify
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13
|
||||
$setup(ADDRARDADDR, posedge CLKARDCLK, 566);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17
|
||||
$setup(ADDRBWRADDR, posedge CLKBWRCLK, 566);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19
|
||||
$setup(WEA, posedge CLKARDCLK, 532);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21
|
||||
$setup(WEBWE, posedge CLKBWRCLK, 532);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L29
|
||||
$setup(REGCEAREGCE, posedge CLKARDCLK, 360);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L31
|
||||
$setup(RSTREGARSTREG, posedge CLKARDCLK, 342);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L49
|
||||
$setup(REGCEB, posedge CLKBWRCLK, 360);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L59
|
||||
$setup(RSTREGB, posedge CLKBWRCLK, 342);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123
|
||||
$setup(DIADI, posedge CLKARDCLK, 737);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133
|
||||
$setup(DIBDI, posedge CLKBWRCLK, 737);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125
|
||||
$setup(DIPADIP, posedge CLKARDCLK, 737);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135
|
||||
$setup(DIPBDIP, posedge CLKBWRCLK, 737);
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143
|
||||
if (&DOA_REG) (posedge CLKARDCLK => (DOADO : 32'bx)) = 2454;
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144
|
||||
if (&DOA_REG) (posedge CLKARDCLK => (DOPADOP : 4'bx)) = 2454;
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L153
|
||||
if (|DOA_REG) (posedge CLKARDCLK => (DOADO : 32'bx)) = 882;
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L154
|
||||
if (|DOA_REG) (posedge CLKARDCLK => (DOPADOP : 4'bx)) = 882;
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163
|
||||
if (&DOB_REG) (posedge CLKBWRCLK => (DOBDO : 32'bx)) = 2454;
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164
|
||||
if (&DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 4'bx)) = 2454;
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L173
|
||||
if (|DOB_REG) (posedge CLKBWRCLK => (DOBDO : 32'bx)) = 882;
|
||||
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L174
|
||||
if (|DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 4'bx)) = 882;
|
||||
endspecify
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,6 +1,3 @@
|
|||
# LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7.
|
||||
# The corresponding mapping file is lutrams_xc5v_map.v
|
||||
|
||||
# Single-port RAMs.
|
||||
|
||||
ram distributed $__ANALOGDEVICES_LUTRAM_SP_ {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,3 @@
|
|||
// LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7, Ultrascale.
|
||||
// The definitions are in lutrams_xc5v.txt.
|
||||
|
||||
|
||||
module $__ANALOGDEVICES_LUTRAM_SP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
|
|
|
|||
|
|
@ -343,10 +343,6 @@ struct SynthAnalogDevicesPass : public ScriptPass
|
|||
params += " -lib +/analogdevices/lutrams.txt";
|
||||
lutrams_map = "+/analogdevices/lutrams_map.v";
|
||||
params += " -lib +/analogdevices/brams.txt";
|
||||
params += " -D HAS_SIZE_36";
|
||||
params += " -D HAS_CASCADE";
|
||||
params += " -D HAS_CONFLICT_BUG";
|
||||
params += " -D HAS_MIXWIDTH_SDP";
|
||||
brams_map = "+/analogdevices/brams_map.v";
|
||||
if (nolutram)
|
||||
params += " -no-auto-distributed";
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue