Krystine Sherwin df95ea824b read_verilog: Add missing defaults for flags ... Fix for YosysHQ/sby#103		2024-05-07 20:25:36 +02:00
..
.gitignore
const2ast.cc
Makefile.inc
preproc.cc	set default_nettype to wire for resetall	2022-08-10 13:28:19 +02:00
preproc.h
verilog_frontend.cc	read_verilog: Add missing defaults for flags	2024-05-07 20:25:36 +02:00
verilog_frontend.h
verilog_lexer.l	fmt: %t/$time support	2023-08-11 04:46:52 +02:00
verilog_parser.y	Resolve struct member multiple dimensions defined in stages with typedef	2024-02-11 11:26:52 -05:00