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yosys/techlibs/anlogic
History
Clifford Wolf 151db528e4 Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-22 18:09:37 +02:00
..
anlogic_eqn.cc
anlogic_fixcarry.cc Proper arith for Anlogic and use standard pass 2019-08-12 20:21:36 +02:00
arith_map.v Fix missing newline at end of file 2019-08-22 18:09:37 +02:00
cells_map.v
cells_sim.v
dram_init_16x4.vh
drams.txt
drams_map.v
eagle_bb.v
Makefile.inc Proper arith for Anlogic and use standard pass 2019-08-12 20:21:36 +02:00
synth_anlogic.cc Proper arith for Anlogic and use standard pass 2019-08-12 20:21:36 +02:00