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.gitignore
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Added tests/various/.gitignore
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2014-07-26 17:43:41 +02:00 |
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attrib05_port_conn.v
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
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attrib05_port_conn.ys
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
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attrib07_func_call.v
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
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attrib07_func_call.ys
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
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chparam.sh
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Add tests/various/chparam.sh
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2019-05-06 16:03:15 +02:00 |
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constmsk_test.v
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Added tests/various/constmsk_test.ys
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2014-09-04 15:07:30 +02:00 |
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constmsk_test.ys
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Added tests/various/constmsk_test.ys
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2014-09-04 15:07:30 +02:00 |
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constmsk_testmap.v
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Added tests/various/constmsk_test.ys
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2014-09-04 15:07:30 +02:00 |
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elab_sys_tasks.sv
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Initial implementation of elaboration system tasks
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2019-05-03 03:10:43 +03:00 |
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elab_sys_tasks.ys
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Initial implementation of elaboration system tasks
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2019-05-03 03:10:43 +03:00 |
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hierarchy.sh
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Fix tests
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2019-04-21 11:40:20 +02:00 |
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muxcover.ys
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Revert "Recognise default entry in case even if all cases covered (fix for #931)"
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2019-04-15 17:52:45 -07:00 |
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muxpack.v
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Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
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2019-06-12 09:01:15 -07:00 |
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muxpack.ys
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Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
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2019-06-12 09:01:15 -07:00 |
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opt_rmdff.v
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Fix init
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2019-05-24 18:43:26 -07:00 |
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opt_rmdff.ys
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Add more tests
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2019-05-24 18:33:18 -07:00 |
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pmux2shiftx.v
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Improvements in pmux2shiftx
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2019-04-20 00:38:25 +02:00 |
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pmux2shiftx.ys
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Updaye pmux2shiftx test
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2019-04-22 16:17:43 +02:00 |
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reg_wire_error.sv
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Modified errors into warnings
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2018-06-05 18:03:22 +03:00 |
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reg_wire_error.ys
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reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
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2018-06-05 18:00:06 +03:00 |
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run-test.sh
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Address requested changes - don't require non-$ name.
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2019-02-22 16:06:10 -08:00 |
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specify.v
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More testing
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2019-05-03 15:54:25 -07:00 |
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specify.ys
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Improve tests/various/specify.ys
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2019-05-06 12:26:15 +02:00 |
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submod_extract.ys
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Added tests/various/submod_extract.ys
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2014-07-26 17:22:18 +02:00 |
