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4d215665a1
Map $macc_v2 cells (one signed <=27x18 product + one <=48-bit addend)
to MULTALU27X18 with the C addend enabled, so a*b+c maps to a single
DSP block instead of a multiply + fabric adder.
The C addend requires DYN_C_SEL("TRUE") + CSEL=1 (gowin_pack reads the
CSEL port, not the C_SEL parameter).
alumacc + macc techmap run before wreduce for gw5a, so $mul and $add
ports still have matching widths when alumacc tries to merge them.
Running after wreduce breaks the merge: wreduce narrows $mul Y (48->45)
but not $add A (stays 48), and alumacc can't merge mismatched widths.
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| .. | ||
| analogdevices | ||
| anlogic | ||
| common | ||
| ecp5 | ||
| efinix | ||
| fabulous | ||
| gatemate | ||
| gowin | ||
| ice40 | ||
| intel_alm | ||
| machxo2 | ||
| microchip | ||
| nanoxplore | ||
| nexus | ||
| quicklogic | ||
| xilinx | ||
| generate_mk.py | ||