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yosys/tests/various
gatecat dd6d34f461 blackbox: Include whiteboxed modules
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 13:58:04 +00:00
..
dynamic_part_select Adding latch tests for shift&mask AST dynamic part-select enhancements 2020-06-09 15:17:01 -05:00
.gitignore Add plugin.so.dSYM to .gitignore 2021-01-18 11:13:21 -07:00
abc9.v
abc9.ys abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
async.sh
async.v
attrib05_port_conn.v
attrib05_port_conn.ys
attrib07_func_call.v tests: fix some test warnings 2020-05-25 10:07:58 -07:00
attrib07_func_call.ys
autoname.ys
blackbox_wb.ys blackbox: Include whiteboxed modules 2021-03-17 13:58:04 +00:00
bug1496.ys
bug1531.ys
bug1614.ys
bug1710.ys
bug1745.ys
bug1781.ys
bug1876.ys
bug2014.ys
chparam.sh
const_arg_loop.sv verilog: fix sizing of constant args for tasks/functions 2021-02-21 15:44:43 -05:00
const_arg_loop.ys verilog: fix sizing of constant args for tasks/functions 2021-02-21 15:44:43 -05:00
const_func.sv verilog: fix sizing of constant args for tasks/functions 2021-02-21 15:44:43 -05:00
const_func.ys verilog: fix sizing of constant args for tasks/functions 2021-02-21 15:44:43 -05:00
const_func_block_var.v Allow localparams in constant functions 2020-08-20 20:10:24 -04:00
const_func_block_var.ys Allow blocks with declarations within constant functions 2020-07-25 10:16:12 -06:00
constcomment.ys
constmsk_test.v
constmsk_test.ys
constmsk_testmap.v tests: fix some test warnings 2020-05-25 10:07:58 -07:00
countbits.sv Add tests for $countbits 2021-02-26 12:28:58 -05:00
countbits.ys Add tests for $countbits 2021-02-26 12:28:58 -05:00
deminout_unused.ys
design.ys
design1.ys
design2.ys
dynamic_part_select.ys Removing trailing whitespace 2020-06-10 10:35:40 -05:00
elab_sys_tasks.sv
elab_sys_tasks.ys
equiv_opt_multiclock.ys
equiv_opt_undef.ys equiv_induct: Fix up assumption for $equiv cells in -undef mode. 2020-07-27 18:36:13 +02:00
exec.ys
fib.v verilog: improved support for recursive functions 2020-12-31 18:33:59 -07:00
fib.ys verilog: improved support for recursive functions 2020-12-31 18:33:59 -07:00
fib_tern.v verilog: support recursive functions using ternary expressions 2021-02-12 14:43:42 -05:00
fib_tern.ys verilog: support recursive functions using ternary expressions 2021-02-12 14:43:42 -05:00
func_port_implied_dir.sv sv: complete support for implied task/function port directions 2020-12-31 16:17:13 -07:00
func_port_implied_dir.ys sv: complete support for implied task/function port directions 2020-12-31 16:17:13 -07:00
gen_if_null.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
gen_if_null.ys verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
global_scope.ys
gzip_verilog.v.gz
gzip_verilog.ys
help.ys
hierarchy.sh
hierarchy_defer.ys
hierarchy_param.ys
ice40_mince_abc9.ys
integer_range_bad_syntax.ys Revert "Revert PRs #2203 and #2244." 2020-07-10 09:59:48 +02:00
integer_real_bad_syntax.ys Revert "Revert PRs #2203 and #2244." 2020-07-10 09:59:48 +02:00
logger_error.ys
logger_nowarning.ys
logger_warn.ys
logger_warning.ys
logic_param_simple.ys Revert "Revert PRs #2203 and #2244." 2020-07-10 09:59:48 +02:00
mem2reg.ys
memory_word_as_index.data Fix elaboration of whole memory words used as indices 2020-12-26 21:47:38 -07:00
memory_word_as_index.v Fix elaboration of whole memory words used as indices 2020-12-26 21:47:38 -07:00
memory_word_as_index.ys Fix elaboration of whole memory words used as indices 2020-12-26 21:47:38 -07:00
muxcover.ys
muxpack.v
muxpack.ys
peepopt.ys peepopt: Remove now-redundant dffmux pattern. 2020-08-07 13:21:34 +02:00
plugin.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
plugin.sh
pmgen_reduce.ys
pmux2shiftx.v
pmux2shiftx.ys
port_sign_extend.v genrtlil: fix signed port connection codegen failures 2021-02-05 19:51:30 -05:00
port_sign_extend.ys genrtlil: fix signed port connection codegen failures 2021-02-05 19:51:30 -05:00
primitives.ys
printattr.ys printattrs: Add test. 2020-05-27 08:00:00 +00:00
rand_const.sv Allow combination of rand and const modifiers 2021-01-21 08:42:05 -07:00
rand_const.ys Allow combination of rand and const modifiers 2021-01-21 08:42:05 -07:00
reg_wire_error.sv
reg_wire_error.ys
run-test.sh tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
scratchpad.ys
script.ys
sformatf.ys
shregmap.v tests: fix some test warnings 2020-05-25 10:07:58 -07:00
shregmap.ys
signed.ys Revert "Revert PRs #2203 and #2244." 2020-07-10 09:59:48 +02:00
signext.ys
sim_const.ys
specify.v
specify.ys verilog: fix specify src attribute 2020-05-04 10:53:06 -07:00
src.ys
submod.ys
submod_extract.ys
sv_defines.ys
sv_defines_dup.ys
sv_defines_mismatch.ys
sv_defines_too_few.ys
sv_implicit_ports.sh
svalways.sh
wreduce.ys
write_gzip.ys
xaiger.ys xaiger: add testcase 2020-05-24 08:48:23 -07:00