Zachary Snow 8de2e863af verilog: support recursive functions using ternary expressions ... This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.		2021-02-12 14:43:42 -05:00
..
dynamic_part_select
.gitignore	Add plugin.so.dSYM to .gitignore	2021-01-18 11:13:21 -07:00
abc9.v
abc9.ys
async.sh
async.v
attrib05_port_conn.v
attrib05_port_conn.ys
attrib07_func_call.v
attrib07_func_call.ys
autoname.ys
bug1496.ys
bug1531.ys
bug1614.ys
bug1710.ys
bug1745.ys
bug1781.ys
bug1876.ys
bug2014.ys
chparam.sh
const_arg_loop.v	Fix constants bound to redeclared function args	2020-12-26 08:48:01 -07:00
const_arg_loop.ys
const_func.v
const_func.ys
const_func_block_var.v	Allow localparams in constant functions	2020-08-20 20:10:24 -04:00
const_func_block_var.ys
constcomment.ys
constmsk_test.v
constmsk_test.ys
constmsk_testmap.v
deminout_unused.ys
design.ys
design1.ys
design2.ys
dynamic_part_select.ys
elab_sys_tasks.sv
elab_sys_tasks.ys
equiv_opt_multiclock.ys
equiv_opt_undef.ys
exec.ys
fib.v	verilog: improved support for recursive functions	2020-12-31 18:33:59 -07:00
fib.ys	verilog: improved support for recursive functions	2020-12-31 18:33:59 -07:00
fib_tern.v	verilog: support recursive functions using ternary expressions	2021-02-12 14:43:42 -05:00
fib_tern.ys	verilog: support recursive functions using ternary expressions	2021-02-12 14:43:42 -05:00
func_port_implied_dir.sv	sv: complete support for implied task/function port directions	2020-12-31 16:17:13 -07:00
func_port_implied_dir.ys	sv: complete support for implied task/function port directions	2020-12-31 16:17:13 -07:00
gen_if_null.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
gen_if_null.ys	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
global_scope.ys
gzip_verilog.v.gz
gzip_verilog.ys
help.ys
hierarchy.sh
hierarchy_defer.ys
hierarchy_param.ys
ice40_mince_abc9.ys
integer_range_bad_syntax.ys
integer_real_bad_syntax.ys
logger_error.ys
logger_nowarning.ys
logger_warn.ys
logger_warning.ys
logic_param_simple.ys
mem2reg.ys
memory_word_as_index.data	Fix elaboration of whole memory words used as indices	2020-12-26 21:47:38 -07:00
memory_word_as_index.v	Fix elaboration of whole memory words used as indices	2020-12-26 21:47:38 -07:00
memory_word_as_index.ys	Fix elaboration of whole memory words used as indices	2020-12-26 21:47:38 -07:00
muxcover.ys
muxpack.v
muxpack.ys
peepopt.ys	peepopt: Remove now-redundant dffmux pattern.	2020-08-07 13:21:34 +02:00
plugin.cc
plugin.sh
pmgen_reduce.ys
pmux2shiftx.v
pmux2shiftx.ys
port_sign_extend.v	genrtlil: fix signed port connection codegen failures	2021-02-05 19:51:30 -05:00
port_sign_extend.ys	genrtlil: fix signed port connection codegen failures	2021-02-05 19:51:30 -05:00
primitives.ys
printattr.ys
rand_const.sv	Allow combination of rand and const modifiers	2021-01-21 08:42:05 -07:00
rand_const.ys	Allow combination of rand and const modifiers	2021-01-21 08:42:05 -07:00
reg_wire_error.sv
reg_wire_error.ys
run-test.sh	tests: Centralize test collection and Makefile generation	2020-09-21 15:07:02 +02:00
scratchpad.ys
script.ys
sformatf.ys
shregmap.v
shregmap.ys
signed.ys
signext.ys
sim_const.ys
specify.v
specify.ys
src.ys
submod.ys
submod_extract.ys
sv_defines.ys
sv_defines_dup.ys
sv_defines_mismatch.ys
sv_defines_too_few.ys
sv_implicit_ports.sh
svalways.sh
wreduce.ys
write_gzip.ys
xaiger.ys