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80bc373519
Fix the failing regression test: the single-fanout passthrough removal was shorting out a cone's only real gate (e.g. a lone $_NOT_ driving an output), replacing it with a bare wire. That drops the gate entirely (nothing left to characterize) and, for an inverter, silently drops the inversion, making the carved cell inequivalent to the RTL. Only short a redundant re-driver whose input is driven by another in-cone cell; keep a passthrough that reads a primary input (the cell-under-test's boundary gate). Also address Greptile review comments: - fix swapped log_warning arguments in the split-boundary-port diagnostic. - error out (instead of silently overwriting) when two cell groups rename to the same carved module name (e.g. slow_<enc> and fast_<enc> -> <enc>). - derive pq_speed from the explicit "fast_" base prefix. Co-authored-by: Cursor <cursoragent@cursor.com> |
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| cmds | ||
| equiv | ||
| fsm | ||
| hierarchy | ||
| memory | ||
| opt | ||
| pmgen | ||
| proc | ||
| sat | ||
| silimate | ||
| techmap | ||
| tests | ||
| CMakeLists.txt | ||