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yosys/frontends/verilog
History
georgerennie c1f6ce8b33 Fix SYNTHESIS always being defined in Verilog frontend
2020-12-01 01:37:19 +00:00
..
.gitignore
const2ast.cc
Makefile.inc Treat all bison warnings as errors in verilog front-end 2020-07-15 11:57:31 +02:00
preproc.cc Fix SYNTHESIS always being defined in Verilog frontend 2020-12-01 01:37:19 +00:00
preproc.h
verilog_frontend.cc Fix SYNTHESIS always being defined in Verilog frontend 2020-12-01 01:37:19 +00:00
verilog_frontend.h
verilog_lexer.l Merge pull request #2179 from splhack/static-cast 2020-07-01 16:40:20 +02:00
verilog_parser.y Ignore empty parameters in Verilog module instantiations 2020-10-01 18:27:16 +02:00