Martin Povišer 0d484818a7 ql_dsp_io_regs: Add DSPv2 support, adjust sim model ... Add support for cell type dispatching of the new DSP block; adjust the definition of MULT and MULTACC variants to support those instances starting a cascading chain.		2025-03-11 16:35:38 +01:00
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.gitignore	quicklogic: Generate bram_types_sim.v at build time	2023-12-04 18:21:00 +01:00
arith_map.v	change ql-bram-types pass to use mode parameter; clean up primitive libraries	2023-12-04 15:52:02 +01:00
brams_map.v	merge brams_final_map.v into brams_map.v	2023-12-04 15:52:02 +01:00
brams_sim.v	quicklogic: Add missing RAM_INIT param on TDP36K sim model	2023-12-04 15:52:03 +01:00
cells_sim.v	quicklogic: Drop blackbox off adder_carry	2023-12-04 15:52:03 +01:00
dspv1_final_map.v	quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged	2025-03-11 10:35:31 +01:00
dspv1_map.v	synth_quicklogic: add -dspv2 to opt into v2 DSP blocks	2025-03-11 10:35:30 +01:00
dspv1_sim.v	quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged	2025-03-11 10:35:31 +01:00
dspv1_sim_extra.v	quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged	2025-03-11 10:35:31 +01:00
dspv2_map.v	quicklogic: update dspv2_sim.v to v1.1 Feb21	2025-03-11 10:35:31 +01:00
dspv2_sim.v	ql_dsp_io_regs: Add DSPv2 support, adjust sim model	2025-03-11 16:35:38 +01:00
ffs_map.v	change ql-bram-types pass to use mode parameter; clean up primitive libraries	2023-12-04 15:52:02 +01:00
generate_bram_types_sim.py	Drop timestamp in generate_bram_types_sim.py	2024-10-30 08:47:18 +01:00
libmap_brams.txt	add qlf_k6n10f architecture + bram inference	2023-12-04 15:52:02 +01:00
libmap_brams_map.v	quicklogic: Test TDP36K inference with initial data	2023-12-04 15:52:03 +01:00
sram1024x18_mem.v	add example memory test	2023-12-04 15:52:03 +01:00
TDP18K_FIFO.v	add example memory test	2023-12-04 15:52:03 +01:00
ufifo_ctl.v	add example memory test	2023-12-04 15:52:03 +01:00