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0b46d8b201
yosys
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frontends
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Akash Levy
bf4ce9d6f7
Import uniquify fix
2026-02-19 00:24:32 -08:00
..
aiger
aiger2
Enable xaiger2 pass when not in NDEBUG
2025-11-21 14:23:32 -08:00
ast
verilog: Do not set
module_not_derived
on internal cells
2026-01-19 16:48:13 -08:00
blif
Merge branch 'YosysHQ:main' into main
2026-02-18 09:44:25 -08:00
json
Support param. default values in JSON FE and SV BE
2026-02-11 08:10:55 -08:00
liberty
read_liberty: support loopy retention cells
2025-11-20 13:21:32 +01:00
rpc
rtlil
Add -legalize option to read_rtlil
2025-12-21 21:47:48 +00:00
verific
Import uniquify fix
2026-02-19 00:24:32 -08:00
verilog
read_verilog: remove log I left behind by accident
2026-01-13 18:47:23 +01:00