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yosys/tests/simple
Zachary Snow f2c2d73f36 sv: fix up end label checking
- disallow [gen]blocks with an end label but not begin label
- check validity of module end label
- fix memory leak of package name and end label
- fix memory leak of module end label
2021-06-16 21:48:05 -04:00
..
.gitignore added more .gitignore files (make test) 2013-01-05 11:35:52 +01:00
aes_kexp128.v
always01.v
always02.v
always03.v
arraycells.v
arrays01.v
arrays02.sv
asgn_binop.sv
attrib01_module.v
attrib02_port_decl.v
attrib03_parameter.v
attrib04_net_var.v
attrib05_port_conn.v.DISABLED
attrib06_operator_suffix.v
attrib07_func_call.v.DISABLED
attrib08_mod_inst.v
attrib09_case.v
carryadd.v
case_expr_const.v
case_expr_non_const.v
const_branch_finish.v
const_fold_func.v
const_func_shadow.v
constmuldivmod.v
constpower.v
defvalue.sv
dff_different_styles.v
dff_init.v
dynslice.v
fiedler-cooley.v
forgen01.v
forgen02.v
forloops.v
fsm.v
func_block.v
func_recurse.v
func_width_scope.v
genblk_collide.v
genblk_dive.v
genblk_order.v
genblk_port_shadow.v
generate.v
graphtest.v
hierarchy.v
hierdefparam.v
i2c_master_tests.v
ifdef_1.v
ifdef_2.v
implicit_ports.v
local_loop_var.sv
localparam_attr.v
loop_var_shadow.v
loops.v
macro_arg_spaces.sv
macro_arg_surrounding_spaces.v
macros.v
matching_end_labels.sv sv: fix up end label checking 2021-06-16 21:48:05 -04:00
mem2reg.v
mem2reg_bounds_tern.v
mem_arst.v
memory.v
module_scope.v
module_scope_case.v
multiplier.v
muxtree.v
named_genblk.v
nested_genblk_resolve.v
omsp_dbg_uart.v
operators.v
param_attr.v
paramods.v
partsel.v
process.v
realexpr.v
repwhile.v
retime.v
rotate.v
run-test.sh
scopes.v
signedexpr.v
sincos.v
specify.v
string_format.v
subbytes.v
task_func.v
undef_eqx_nex.v
unnamed_block_decl.sv
usb_phy_tests.v
values.v
verilog_primitives.v
vloghammer.v
wandwor.v
wreduce.v
xfirrtl