yosys/tests/various/setundef_selection_undriven.v at main - mirrors/yosys - Libre-Chip.org

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abhinavputhran 314d01b35f changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change

2026-03-08 20:14:03 -04:00

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Verilog

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 module test;
     wire a;
     wire b;
 endmodule