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yosys/tests
George Rennie 0fcf5c080d
Merge pull request #5158 from georgerennie/george/task_inout
read_verilog/astsimplify: copy inout ports in and out of functions/tasks
2025-06-04 14:23:08 +01:00
..
aiger aiger: add regression test for sliced output segfault 2025-05-09 16:01:47 +02:00
alumacc macc_v2: Add test 2025-01-27 13:19:26 +01:00
arch URAM mapping : Add test for 2048 x 144b 2025-05-10 14:53:56 +02:00
asicworld tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
bind Add support for parsing the SystemVerilog 'bind' construct 2021-07-16 09:31:39 -04:00
blif tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
bram tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
cxxrtl Reinstate #4768 2025-04-08 11:58:05 +12:00
errors Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 2018-10-25 02:37:56 +03:00
fmt cxxrtl: always lazily format print messages. 2024-01-19 18:55:23 +00:00
fsm tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
functional functional tests: run from make tests but not smtlib/rkt tests 2024-09-04 10:30:08 +01:00
hana tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
liberty libcache: fix test 2025-05-09 12:40:38 +02:00
lut tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
memfile tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
memlib Move parameters to module declaration 2024-04-08 12:44:37 +02:00
memories rtlil: Adjust internal check for $mem_v2 cells 2024-11-08 15:18:43 +01:00
opt tests: test opt_expr for 32 bit unsigned shifts 2025-05-26 15:28:44 +01:00
opt_share tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
peepopt Add muldiv_c peepopt pass 2025-04-30 08:06:59 -07:00
proc Merge pull request #4714 from georgerennie/george/proc_dff_bug_multiple_sigs 2024-11-20 13:26:32 +01:00
realmath tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
rpc Remove references to ilang 2024-11-05 12:36:31 +13:00
sat share: Cleanup and additional testing 2025-04-15 12:34:46 +02:00
select design.cc: Fix selections when copying 2025-04-08 16:35:12 +12:00
share tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
sim fstdata.cc: Fix last step 2025-05-12 13:18:19 +12:00
simple write_verilog: don't assign to a reg. 2024-04-03 13:06:45 +02:00
simple_abc9 Reinstate #4768 2025-04-08 11:58:05 +12:00
smv Remove references to ilang 2024-11-05 12:36:31 +13:00
sva tests/sva: Skip sva tests that use SBY until SBY is compatible again 2024-03-05 14:37:33 +01:00
svinterfaces tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
svtypes Tests: Add svtypes/typedef_struct_global.ys 2025-05-26 12:16:58 +12:00
techmap Add check at constmap and merge test 2025-04-14 11:44:52 +01:00
tools support file locations containing spaces 2022-08-08 20:30:50 +02:00
unit rtlil: Add {from,to}_hdl_index methods to Wire 2025-02-18 17:08:45 +01:00
various cutpoint: Re-add whole module optimization 2025-05-06 09:57:34 +12:00
verific Merge pull request #4814 from YosysHQ/emil/make-test-fasterer 2024-12-18 19:02:39 +01:00
verilog Merge pull request #5158 from georgerennie/george/task_inout 2025-06-04 14:23:08 +01:00
vloghtb tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
xprop tests: Comment on A[0] 2024-02-16 11:43:28 +01:00
gen-tests-makefile.sh Update gen-tests-makefile.sh 2025-03-27 10:33:51 +13:00