mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-07 05:06:27 +00:00
Code Activity
yosys/techlibs/gatemate
History
Exact
Lofty 09dd419183 wip
2025-06-07 02:06:42 +01:00
..
.gitignore gatemate: Add LUT tree library script 2022-06-27 10:09:48 +01:00
arith_map.v synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
brams.txt gatemate: WRITE_THROUGH mode change 2025-04-18 14:16:02 +02:00
brams_init_20.vh synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
brams_init_40.vh synth_gatemate: Revise block RAM read modes and initialization 2021-11-13 21:53:25 +01:00
brams_map.v gatemate: Set unused BRAM inputs to 'bx 2025-04-28 14:42:16 +02:00
cells_bb.v gatemate: Add CC_SERDES parameters and update port names 2025-01-10 10:25:10 +01:00
cells_sim.v wip 2025-06-07 02:06:42 +01:00
gatemate_foldinv.cc rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
inv_map.v gatemate: Add LUT tree library script 2022-06-27 10:09:48 +01:00
lut_map.v synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
make_lut_tree_lib.py wip 2025-06-06 11:04:38 +01:00
Makefile.inc gatemate: Add LUT tree library script 2022-06-27 10:09:48 +01:00
mul_map.v synth_gatemate: Rename multiplier factor parameters 2021-11-13 21:53:25 +01:00
mux_map.v synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
reg_map.v gatemate: Enable register initialization 2023-02-15 17:29:01 +01:00
synth_gatemate.cc wip 2025-06-07 02:06:42 +01:00